Device having an interface and method thereof

Details Device having an interface and method thereof Device having an interface and method thereof

2007-03-06

2007-03-06

Le, Vu A. (Department: 2824)

Static information storage and retrieval

Read/write circuit

Signals

C365S233100

Reexamination Certificate

active

11098873

ABSTRACT:
A system device receives a first data signal and a first strobe signal from a dual-data-rate (DDR) memory. A first delay value representative of a delay to a predetermined phase location of the first strobe signal is determined. The first delay is adjusted based on a first offset value to generate a first adjusted delay value used to delay the first strobe signal. A first edge of a first pulse of the first delayed strobe signal is used to latch a first data value of the first data signal.

REFERENCES:
patent: 6889334 (2005-05-01), Magro et al.
patent: 6940768 (2005-09-01), Dahlberg et al.
Lau, William, “Design Feature: Overcoming DDR-2-Interface Challenges,” LSI Logic, pp. 71-74, <http://www.edn.com>>, Jan. 22, 2004.

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