Static information storage and retrieval – Read/write circuit – Including signal comparison
Reexamination Certificate
2002-02-13
2004-07-20
Lebentritt, Michael S. (Department: 2824)
Static information storage and retrieval
Read/write circuit
Including signal comparison
C365S207000, C365S230060
Reexamination Certificate
active
06765829
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to a device having a processor and a memory element arranged outside the processor, as well as a memory element.
BACKGROUND INFORMATION
Control units for controlling operating sequences, specifically in a vehicle, are known. These are, for example, control units for controlling valve timing, brakes, transmission, etc. The digital components contained in the control units, in addition to the processor, or the computer, which contains an internal memory, also include external memories, which are connected via a printed-circuit board to the computer, or processor. Coupling the external memories to the processor is generally accomplished using a printed-circuit board. The connection via printed-circuit boards, however, represents a limitation on the working frequency of the coupling, because the latter represents both a capacitative as well as an inductive load. The efficiency of this connection, i.e., between the computer and the external memory, specifically the transmission rate, has a direct effect upon the overall efficiency of the system, in relation to the respective control system.
To achieve increased efficiency, modern connecting configurations such as in SDRAM (Synchronous Dynamic RAM) are known, which permit an increase in the frequency, albeit having the above-mentioned limitation. A further problem in the case of these connections is that they were developed for relatively long distances between computers and memories and therefore, within certain parameters, cannot achieve a higher frequency.
Further increases in the pulse frequency of the connection between the computer and the external memory are promised by technologies such as DDRRAM (Double Data Rate RAM), which are superimposed on the above-mentioned SDRAM, as well as RAMBUS technologies such as RDRAM (Rambus DRAM) or DRDRAM (Direct Rambus Dynamic RAM).
A further problem that arises in the context of increasing the connecting frequency is the radiation, i.e., the coupling of electromagnetic signals or energy, as a result of which, at higher pulse frequencies, greater expense is necessary in designing an adequate screening, in order to meet, for example, the legal requirements and also to prevent an undesirable coupling of signals.
However, it has been demonstrated that the related art has not been able to supply optimal results in every respect.
In addition, in another technical area, buses or bus systems are known as a point-to-point connections for the coupling of devices to a computer, which are represented in an LVDS (low voltage differential signal) structure. This LVDS structure is familiar as a standard in accordance with ANSI/TIA/EIA-644. According to this standard, LVDS acts as a communications connection, for example, between a computer and an associated video screen.
Furthermore, the IEEE standard P1596.3-1995 defines the aforementioned LVDS as a communications connection between processors in multi-processor systems, a point-to-point connection being represented here in half-duplex operation so as to be also bidirectional.
SUMMARY OF THE INVENTION
It is proposed to use the LVDS (low voltage differential signal) structure for coupling external memories to a processor, or computer. In this context, one initial result is the increased expense in comparison to conventional external memory connections, mainly because the number of leads per data bit is doubled from one to two. However, as a result, a significantly higher transmission rate is unexpectedly achieved in comparison to the conventional external memory connections, as a result of which this connection and therefore the entire system achieves greater efficiency. The result is a memory element which can be connected to a processor via address and/or data lines, the memory element being arranged outside the processor and the address and/or data lines being configured in each case in an LVDS structure using appropriate drivers and receivers, the drivers and receivers being integrated in the memory element.
Another result is a device having a processor and a memory element arranged outside the processor, the processor and the memory element being connected via address and/or data lines, and the address and/or data lines, in each case, being configured in an LVDS structure using corresponding drivers and receivers.
In addition to the increased efficiency, specifically in the transmission rate, the improved radiation protection with respect to signals, provided by the differential structure, can also be exploited in this context. Similarly, as a result of using smaller bus voltages, the radiation at the same pulse frequency is smaller due to the smaller signal deviation.
It is also advantageous that it is easier to adapt to new technologies as a result of the differential principle, because no power-supply dependency exists on the bus.
As a result of the parallel use of the LVDS structure, which is intrinsically provided as a point-to-point connection, the throughput over the connection between the computer and the external memory is substantially increased so that the computer, or processor, can adequately fetch, i.e., receive or retrieve, instructions even at higher pulse frequencies or transmission rates.
In this manner, systems, specifically control systems, for controlling operating sequences in a vehicle, can attain comparable efficiency from the external memory, in particular, from an external flash, such as heretofore has been possible only from the internal memory, specifically an internal flash. However, if in the case of the internal memory the advantage of higher efficiency, specifically the transmission rate, falls away, then for cost reasons, it is expedient to use only an external memory, specifically an external flash, which is linked by an LVDS structure to the computer, or processor.
It is also advantageous that the address information can be transmitted over this LVDS connection, and that therefore the efficiency, in particular the transmission rate, or the velocity, can be further increased, or the pin count for the bus interface can be raised.
REFERENCES:
patent: 5479123 (1995-12-01), Gist et al.
patent: 6151648 (2000-11-01), Haq
patent: 6160423 (2000-12-01), Haq
patent: 2002/0011998 (2002-01-01), Tamura
Aue Axel
Graf Jens
Thomas Martin
Kenyon & Kenyon
Lebentritt Michael S.
Nguyen Tuan T.
Robert & Bosch GmbH
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