Static information storage and retrieval – Read/write circuit – Data refresh
Reexamination Certificate
2005-10-25
2005-10-25
Mai, Son (Department: 2827)
Static information storage and retrieval
Read/write circuit
Data refresh
C365S200000, C365S230040, C365S230060
Reexamination Certificate
active
06958945
ABSTRACT:
A memory array is provided, having at least two memory cells accessed for each row address to retain a sufficient electric charge to properly store “1” and “0” bits. For such a memory array, both even and odd row decoders in the array are permanently enabled so that each row address the array receives causes the even row decoder to energize at least one even word line and the odd row decoder to energize at least one odd word line. As a result, at least two memory cells are accessed for each row address so that each “1” or “0” bit is stored as an electric charge in at least two memory cells.
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