Device forming a logic gate for detecting a logic error

Electronic digital logic circuitry – Function of and – or – nand – nor – or not

Reexamination Certificate

Rate now

  [ 0.00 ] – not rated yet Voters 0   Comments 0

Details

C326S103000, C326S009000, C326S014000

Reexamination Certificate

active

08030970

ABSTRACT:
The invention relates to a device for forming an electric circuit comprising logic means (30) generating and using small signals of intermediate levels between the device supply levels and means for detecting signals leaving the small signal range.

REFERENCES:
patent: 4947105 (1990-08-01), Unger et al.
patent: 5043604 (1991-08-01), Komaki
patent: 5187392 (1993-02-01), Allen
patent: 5365123 (1994-11-01), Nakase et al.
patent: 5491432 (1996-02-01), Wong et al.
patent: 5585744 (1996-12-01), Runas et al.
patent: 7372303 (2008-05-01), Akiyoshi
patent: 2004/0041612 (2004-03-01), Huber
patent: 2005/0046442 (2005-03-01), Song
patent: 2006/0232294 (2006-10-01), Song
patent: 2007/0170954 (2007-07-01), Akiyoshi
patent: 0768671 (1997-04-01), None
International Search Report, PCT/EP2006/062917.
“Advanced Encryption Standard (AES)”, Federal Information Processing Standards Publication 197, http://csrc.nist.gov/encryption/aes/index/html, Nov. 26, 2001, pp. i-iv, pp. 1-47.
Biham et al., “Differential Fault Analysis of Secret Key Cryptosystems”, Proceedings of Advances in Cryptology (CRYPTO), 1997, pp. 513-525.
Dusart et al., “Differential Fault Analysis on A.E.S.”, Cryptology ePrint Archive 2003/010 http://www.iacr.org., Jan. 10, 2002, pp. 1-10.
Bar-El et al., “The Sorcerer's Apprentice Guide to Fault Attacks”, Proceedings of Workshop on Fault Detection and Tolerance in Cryptolograph, 2004.
Sparso et al., “Principles of Asynchronous Circuits Design”, 2001, Kluwer Academic Publishers, pp. 11-23.
Moore et al., “Improving Smart Card Security Using Self-Timed Circuits”, Proceedings of the Eighth International Symposium on Asynchronous Circuits and Systems, 2002.

LandOfFree

Say what you really think

Search LandOfFree.com for the USA inventors and patents. Rate them and share your experience with other people.

Rating

Device forming a logic gate for detecting a logic error does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Device forming a logic gate for detecting a logic error, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Device forming a logic gate for detecting a logic error will most certainly appreciate the feedback.

Rate now

     

Profile ID: LFUS-PAI-O-4303190

  Search
All data on this website is collected from public sources. Our data reflects the most accurate information available at the time of publication.