Electrical computers and digital data processing systems: input/ – Input/output data processing – Input/output data buffering
Reexamination Certificate
2007-02-27
2007-02-27
Peyton, Tammara (Department: 2182)
Electrical computers and digital data processing systems: input/
Input/output data processing
Input/output data buffering
C710S050000, C710S051000, C710S057000, C710S267000, C712S225000, C712S228000
Reexamination Certificate
active
10743564
ABSTRACT:
Device for transferring data between two asynchronous systems communicating via a FIFO memory. The first system comprises a write pointer register and the second system comprises a read pointer register to the FIFO. Each pointer register is associated with a primary shadow register and a secondary shadow register. The primary shadow register is located in the same sub-assembly as the pointer register with which it is associated, and episodically receives a copy of this pointer register. The secondary shadow register is located in the other sub-assembly, and episodically receives a copy of the primary shadow register. Thus, each system has its own pointer register, its associated primary shadow register, and the secondary shadow register associated with the pointer register of the other system.
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Iannucci Robert
Jorgenson Lisa K.
Peyton Tammara
Seed IP Law Group PLLC
STMicroelectronics S.A.
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