Electrical computers and digital processing systems: memory – Address formation – Generating prefetch – look-ahead – jump – or predictive address
Patent
1998-03-13
2000-10-24
Gossage, Glenn
Electrical computers and digital processing systems: memory
Address formation
Generating prefetch, look-ahead, jump, or predictive address
711218, 711109, 365 73, 365240, G06F 1202, G11C 804
Patent
active
061382272
DESCRIPTION:
BRIEF SUMMARY
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a device for the jump-like addressing of specific lines of a serially operating digital memory.
2. Description of the Related Art
Serially operating memories comprise a memory matrix consisting of memory cells arranged in rows and columns in a matrix form and decoders or other control devices, for example control chains (see, for example, the German Patent Application P 195 12 791.9, which are also called pointers.
The memory matrix contains, in addition to the memory cells, bit lines and word lines running at right angles to the latter. Each memory cell is connected to a bit line and is driven by a word line.
If a word line is addressed by a word decoder or, for example, by a word control chain or pointer, that is to say if it is selected, then the memory cells on this word line deliver their information to the bit lines assigned to them. Subsequently, via a bit decoder or, for example, a bit control chain, one of the bit lines and hence the information of a specific memory cell is addressed, that is to say selected.
In sequentially operating memories, this process takes place continuously, so that all the memory cells are addressed consecutively. However, in order to obtain information from the memory which can be corrected as far as possible (redundant codes), the cells of one word line or bit line must not be read out directly one after the other. In the case of completely faulty bit lines or word lines, the information content of the memory cell could in this case no longer be corrected. However, failures of adjacent word lines and bit lines occur very frequently. It is therefore beneficial to arrange the bit decoders or word decoders or control chains in such a way that they never drive the directly adjacent lines when the selection lines are changed. Such a method is designated here as, in particular, sequential, jump-like addressing.
Using the normal binary decoders, this jump-like addressing can be achieved in several ways: continuously but with regular jumps. fed to a decoder is increased continuously, outputs from the decoder are jumped over at regular intervals. address. Because of the binary addresses, such a division of the address permits only group sizes which are an integer part of all the lines to be selected, otherwise not all the lines are selected or some addresses select no lines, so that so-called empty addresses are produced. If it is intended to achieve jumps which are an integer part of all the lines to be selected, then the binary address must be increased using these jumps. This condition is required for serially operated memories see the abovementioned German reference P 195 12 791.9).
SUMMARY OF THE INVENTION
As a result of the device described below, for the jump-like addressing of specific lines of a serially operating digital memory, any arbitrary jump increments can advantageously be implemented. In particular, the invention provides a device for the jump-like addressing of specific lines of a serially operating digital memory, having two control devices which are jointly assigned to the specific lines, each of the control devices having a plurality of outputs and, at the outputs, chronologically successively generates a specific binary information item assigned to the respective the control device and decisive for addressing one of the specific lines, a plurality of linking elements, each of the linking elements being assigned to one of the specific lines and having an output assigned to this specific line, the linking elements each having an input assigned to one of the two control devices as well as an input assigned to an other one of the two control devices, each of the linking elements addressing precisely the one of the specific lines assigned to it alone via its output precisely when there is present at its input assigned to the one control device the specific binary information item assigned to the control device and, simultaneously, there is present at its input assigned to
REFERENCES:
patent: 5444660 (1995-08-01), Yamanaka et al.
patent: 5751742 (1998-05-01), Von Basse et al.
Japanese Abstract, vol. 7, No. 266, 58-146080.
Bollu Michael
Schmitt-Landsiedel Doris
Thewes Roland
VON Basse Paul-Werner
Gossage Glenn
Siemens Aktiengesellschaft
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