Active solid-state devices (e.g. – transistors – solid-state diode – Housing or package – With provision for cooling the housing or its contents
Reexamination Certificate
2000-08-04
2003-03-04
Talbott, David L. (Department: 2827)
Active solid-state devices (e.g., transistors, solid-state diode
Housing or package
With provision for cooling the housing or its contents
C257S717000, C257S720000, C257S724000, C257S730000, C361S689000, C361S699000, C361S702000, C361S703000, C361S710000, C361S711000, C361S718000
Reexamination Certificate
active
06528878
ABSTRACT:
CROSS-REFERENCES TO RELATED APPLICATIONS
This application claims priority from Japanese Patent Application Reference No. 11-222058, filed Aug. 5, 1999.
BACKGROUND OF THE INVENTION
The present invention relates generally to integrated circuit chips with semiconductor elements, and more specifically for large scale integrated circuit chips with semiconductor elements that provide high speeds, high integration, high heat-generation density, high power dissipation, and large dimensions for use in large-scale computers or supercomputers.
In computers, such as large-scale computers and supercomputers, increased processing throughput and storage capacity is achieved by higher speeds, greater integration, larger dimensions, and higher thermal density in large-scale integrated circuits with semiconductor elements (hereinafter abbreviated as LSIs). Also, in order to transfer signals at high-speeds between multiple LSIs, the electrical connections between the multiple LSIs must be made as short as possible. This need is met with multi-chip modules in which multiple LSIs are densely mounted on a multi-layer circuit substrate. Thus, providing a cooling mechanism to assure stable operations of the LSIs, and providing a tight sealing mechanism to reliably protect the LSIs from the outside environment are important technical issues for multi-chip modules.
What is needed are better techniques for sealing and cooling multi-chip modules.
SUMMARY OF THE INVENTION
According to the present invention, techniques for sealing and cooling multi-chip modules equipped with a cooling mechanism are provided. Embodiments according to the invention can provide a reliable, tight seal for multi-chip modules with a high-density arrangement of multiple integrated circuit chips with semiconductor elements. Techniques according to the invention can eliminate, with a low thermal resistance, the heat generated by multiple integrated circuit chips with semiconductor elements. Embodiments according to the present invention can be especially useful when applied to integrated circuit chips with semiconductor elements, and more specifically for integrated circuit chips with semiconductor elements that provide high speeds, high integration, high heat-generation density, high power dissipation, and large dimensions for use in large-scale computers or supercomputers.
In a representative embodiment according to the present invention, there is provided a multi-chip module sealing/cooling device equipped with a multi-chip module cooling mechanism that uniformly and efficiently lowers the temperature of LSIs formed with high integration, high heat-generating density, large dimensions, high power dissipation, and dense mounting.
Further, in another representative embodiment according to the present invention, there is provided a multi-chip module sealing/cooling device equipped with a multi-chip module sealing mechanism that is easy to assemble and disassemble and that provides long-term, reliable protection for the LSIs, for example.
In a representative embodiment according to the present invention, there is provided a multi-chip module sealing/cooling device in which a sealing top plate of a multi-chip module, on which is formed cooling flow path grooves, that is directly soldered to the LSI chips or a back surface of a semiconductor device such as an LSI package containing an LSI chip.
Embodiments according to the present invention can also provide a multi-chip module sealing/cooling device in which a lowered offset is formed at the edge of the back surface of the LSI package containing the LSI chip. In a specific embodiment, this offset can be approximately 500 micrometers, measured from the back surface of the device, for example. Other embodiments can have other size offsets as well. This controls the area used for the solder bond formed on the sealing top plate of the multi-chip module, on which is formed a cooling flow path groove.
Embodiments according to the present invention can also provide a multi-chip module sealing/cooling device in which the sealing top plate of the multi-chip module, on which is formed a cooling flow path groove, is formed from a ceramic having a high thermal conductivity having a thermal expansion coefficient consistent with that of the multi-layer circuit substrate. A cooling flow path cover covering the entire area of the cooling flow path groove is formed as a separate member. Thus, the thermal capacity of the sealing top plate is reduced for when a solder bond is formed with the back surface of the semiconductor device such as an LSI chip or an LSI package containing an LSI chip.
Embodiments according to the present invention can also provide a multi-chip module sealing/cooling device in which the sealing top plate, on which a cooling flow path groove is formed, is formed from a ceramic having a high thermal conductivity. A cooling flow path cover covering the entire area of the cooling flow path groove is formed from a metallic material. A tightening means interposes a sealing material such as an O-ring between the edge of the sealing top plate and the cooling flow path cover and tightens together the metallic cooling flow path cover and a sealing frame of the multi-chip module. This maintains the strength of the ceramic sealing top plate while preventing leakage of the cooling fluid and also increasing the strength of pipe connections that allow cooling fluid to flow in and out of the cooler.
In a representative embodiment according to the present invention, a device for sealing and cooling multi-chip modules is provided. The multi-chip modules can comprise a circuit substrate having a plurality of semiconductor devices mounted thereon, and a frame. The frame fixed to the circuit substrate and formed from a material having a thermal expansion coefficient consistent with a thermal expansion coefficient of the circuit substrate. The device can comprise a sealing top plate, a first surface thereof being formed with a cooling flow path, a second surface thereof being bonded to a back surface of the semiconductor devices, and an edge thereof, joining the frame to form a first seal. The sealing top plate can be formed from a ceramic having a high thermal conductivity and a thermal expansion coefficient consistent with that of the multi-layer circuit substrate, for example. The back surface of the sealing top plate can be bonded directly to the back surface of the semiconductor devices using solder, for example, in order to provide a thermal conductive path having a low thermal resistance. A cooling flow path cover for covering the cooling flow path can also be provided. The cooling flow path cover can be metallic, or the like. A sealing material for preventing leakage of a cooling fluid from the cooling flow path can be provided. The sealing material interposed between the edge of the sealing top plate and the cooling flow path cover to form a second seal. The sealing material can be an O-ring, and the like, for example. A tightening means, such as a plurality of bolts, for example, can be used to tighten together the cooling flow path cover, the sealing material, the sealing top plate and the frame. An area formed by the top surface of the circuit substrate, the bottom surface of the sealing top plate and the first seal can be filled with nitrogen gas, for example.
In another representative embodiment according to the present invention, a method for sealing multi-chip modules is provided. The method is useful with multi-chip modules comprising a circuit substrate having a plurality of semiconductor devices mounted thereon, and a frame, for example. The frame can be fixed to the circuit substrate and formed from a material having a thermal expansion coefficient consistent with a thermal expansion coefficient of the circuit substrate. The method comprises forming onto a first surface of a sealing top plate a cooling flow path. Bonding a second surface of the sealing plate to a back surface of the semiconductor devices can also be part of the method. Further, the method can include joining an ed
Daikoku Takahiro
Kasai Kenichi
Koyano Koichi
Netsu Toshitada
Uda Takayuki
Chambliss Alonzo
Talbott David L.
Townsend and Townsend / and Crew LLP
LandOfFree
Device for sealing and cooling multi-chip modules does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Device for sealing and cooling multi-chip modules, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Device for sealing and cooling multi-chip modules will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3037301