Active solid-state devices (e.g. – transistors – solid-state diode – Housing or package
Reexamination Certificate
1998-06-05
2001-05-29
Whitehead, Jr., Carl (Department: 2822)
Active solid-state devices (e.g., transistors, solid-state diode
Housing or package
C257S737000, C257S778000
Reexamination Certificate
active
06239481
ABSTRACT:
RELATED APPLICATIONS
This application is related to the co-filed and commonly assigned applications; Ser. No. 09/092,674, filed Jun. 5, 1998, now U.S. Pat. No. 6,139,403, issued Oct. 31, 2000, entitled “Method and Device for Accessing Flip Chip Circuitry,” 09/092,674, filed Jun. 5, 1998 entitled “Method and Device for Supporting Flip Circuitry under Analysis,” 09/090,447, filed Jun. 4, 1998 entitled “An Alternate Method and Device for Removing A Flip Chip Die From Packaging,” 09/092,164, filed Jun. 5, 1998 entitled “A Method and Device for A Flip Chip Die and Package Holder,” which are hereby incorporated by reference.
1. Field of the Invention
The invention relates to semiconductor device assemblies, and more particularly to techniques for analyzing and debugging circuitry associated with a flip chip bonded integrated circuit.
2. Background of the Invention
The semiconductor industry has seen tremendous advances in technology in recent years which have permitted dramatic increases in circuit density and complexity, and equally dramatic decreases in power consumption and package sizes. Present semiconductor technology now permits single-chip microprocessors with many millions of transistors, operating at speeds of tens (or even hundreds) of MIPS (millions of instructions per second) to be packaged in relatively small, air-cooled semiconductor device packages. A by-product of such high-density and high functionality in semiconductor devices has been the demand for increased numbers of external electrical connections to be present on the exterior of the die and on the exterior of the semiconductor packages which receive the die, for connecting the packaged device to external systems, such as a printed circuit board.
Flip chip technology answers the demand for improved input/output (I/O) connections from the chip to external systems. On a flip chip, the electrical components are located (face down) on the side of the die which attaches to the chip package. In this manner, the flip chip provides a short interconnection length using, for example, ball-grid array (BGA) solder connections. The self-aligning nature of the solder bumps offers the advantages of higher density mounting, improved electrical performance and reliability, and better manufacturability. The positioning of the circuit side is the source of many advantages in the flip chip design. However, in other regards, the orientation of the die with the circuit side face down on a substrate is a disadvantage.
In example, access to the circuit region is sometimes necessitated in order to modify or debug a finished chip. Additionally, access to the circuit region is often required through manufacturing stages in order to test and analyze circuit's integrity. In this event, it is necessary to burrow through the body of the flip chip die or through the chip package in order to access the circuit region.
Various methods have been employed to quickly and effectively access the circuit region. A popular method includes milling or grinding off portions of the die, or the chip packaging in order to burrow through to the circuit region. The difficulty lies in the accuracy of this method. Since the circuit region is formed in a very thin epitaxial layer, with a typical thickness of only 10-20 micrometers (&mgr;m), an overshoot in the milling process can grind through the very circuit for which the testing was intended. Conversely, slowly milling off portions of the chip package is inefficient for mass fabrication procedures.
For these reasons, it is necessary to uncover an alternative method and device for accessing the circuit region on a flip chip die. The new method and device should desirably permit multiple portions of the circuit region to be analyzed, yet leave the circuit region in a useable condition. A new method and device would similarly be desirable in which the circuit region could be debugged and then placed back in operation. Any work performed on the circuit should leave other portions of the circuit region intact so that they can be the subject of later analysis.
SUMMARY OF THE INVENTION
The above mentioned problems with integrated circuit technology and other problems are addressed by the present invention and will be understood by reading and studying the following specification. A device and method are described which accord these benefits.
In particular, an illustrative embodiment of the present invention includes a method for removing a flip chip die from a chip package. The method includes removing portions of the chip package from outside a circuit region of the flip chip die. A silicon carcass from a discarded die is attached as a backplate to the flip chip die. Heat is applied to the chip package. Then, the flip chip die is removed from the chip package.
In another embodiment, a device for accessing a circuit region on a flip chip die is provided. The device includes a chip package. The chip package has electrical connections to the circuit region. The chip package has no electrical pin connections for external device connection. A silicon carcass from a discarded die is attached as a backplate to the flip chip die. A heat source is in contact with the chip package.
In an alternative embodiment, a system for accessing a circuit region on a flip chip die is provided. The system includes a device for accessing the circuit region. The device includes a chip package. The chip package has electrical connections to the circuit region. The chip package has no electrical pin connections for external device connection. A silicon carcass from a discarded die is attached as a backplate to the flip chip die. A heat source is in contact with the chip package. The system further includes a controller which electrically couples to the heat source for controlling the operation of the heat source.
Thus an alternative method and device for accessing the circuit region on a flip chip die are provided. The new method and device facilitates the analysis of multiple portions of the circuit region and leaves other portions of the circuit intact such that they can later be analyzed. Access to the circuit region is gained without deteriorating any portions of the circuit region through the process. In a similar fashion, the new method and device allow for the circuit region to be modified, or “debugged,” and then returned into operation.
These and other embodiments, aspects, advantages, and features of the present invention will be set forth in part in the description which follows, and in part will become apparent to those skilled in the art by reference to the following description of the invention and referenced drawings or by practice of the invention. The aspects, advantages, and features of the invention are realized and attained by means of the instrumentalities, procedures, and combinations particularly pointed out in the appended claims.
REFERENCES:
patent: 5147084 (1992-09-01), Behun et al.
patent: 5475236 (1995-12-01), Yoshizaki
Advanced Micro Devices , Inc.
Jr. Carl Whitehead
Potter Roy
LandOfFree
Device for removing a flip chip die from packaging does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Device for removing a flip chip die from packaging, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Device for removing a flip chip die from packaging will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2488541