Electrical computers and digital processing systems: support – Clock control of data processing system – component – or data...
Reexamination Certificate
1998-07-10
2001-03-13
Lee, Thomas C. (Department: 2787)
Electrical computers and digital processing systems: support
Clock control of data processing system, component, or data...
C713S400000, C713S503000, C713S600000
Reexamination Certificate
active
06202168
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a method for transferring a data signal between pluralities of logic circuits. More specifically, the present invention relates to a method of regulating the delay time of a transferred data signal between the logic circuits.
2. Description of the Related Art
In a logic device, such as a computer, the operation of logic circuits involves sending and/or receiving data signals between the logic circuits in synchronism with a system clock signal. In order for those logic circuits to operate normally, it is necessary for the transferred data signal to reach the designated logic circuit within a predetermined time.
FIG. 6
is a diagram of a logic circuit of the prior art in which a data signal is transferred between the logic circuits. As shown, there is a logic circuit
601
on the sending side and a logic circuit
602
on the receiving side. The logic circuits
601
and
602
are formed in an integrated circuit. The logic circuit
601
includes a flip-flop circuit
603
and a driver circuit for signal transfer
604
. The logic circuit
602
includes a transferred signal input circuit
606
and a flip-flop circuit
608
. There is a signal transferring circuit
605
between the logic circuits
601
and
602
. The system clock signal (CLK) is supplied from a common clock signal source
609
to the flip-flop circuit
603
of the logic circuit
601
, the flip-flop circuit
608
of the logic circuit
602
, and the data signal is transferred in synchronism with the system clock signal (CLK).
FIG. 7
is a timing chart showing the timing of the signals associated with the data transfer between the logic circuits
601
and
602
of FIG.
6
. Signal CLK is the system clock signal, signal Q
1
is an output signal of the flip-flop circuit
603
, signal OUT is an output signal of output circuit
604
, signal IN is an input signal of input circuit
606
, signal D
2
is an input signal of the flip-flop circuit
608
and signal Q
2
is an output signal of the flip-flop circuit
608
.
With reference to
FIG. 7
, the design objective is to output signal Q
2
from the flip flop circuit
608
three cycles of the system clock after signal Q
1
is output from the flip-flop circuit
603
. In the figure, the system clock cycle is Tck and the delay time from the signal Q
1
to the signal D
2
is Td. The desired delay time of the circuits
603
,
604
,
605
and
606
may be expressed by equation (1).
2Tck<Td≦3Tck (1)
However, if the delay time of the circuits
603
,
604
and
606
and the delay time of the wiring circuitry used for the circuit
605
vary, for example due to the deviations in the manufacturing processes for the respective circuits, a difficulty occurs in the normal transfer of data signals because equation (1) is not satisfied.
FIG. 8
shows an example of a case in which the delay time of the circuits and wiring, etc. varies by &Dgr;Td in the direction of decreasing the delay time for the respective circuits. As another example, the delay time could be varied by &Dgr;Td in the direction of increasing the delay time, although only the decreasing delay time example is shown in the figure. To solve the above problem, it is necessary to measure the delay time Td for all elements affecting the data signal transfer and regulate the delay time Td to satisfy equation (1). However, this objective is impractical to realize because normal logic devices have a great number of signal lines which would need to be regulated.
One attempt for solving such prior art problems related to the difficulty of accomplishing normal data transfer due to the variations in data transfer time between logic circuits is disclosed, for example, in the HP Journal, August 1992, page 14. In the article, a method is disclosed for transferring a clock signal from a logic circuit on a sending side to a logic circuit on a receiving side in parallel with a transferred data signal.
FIG. 9
is a circuit diagram showing the configuration of a clock signal parallel transfer method used in the prior art and includes a logic circuit
901
on the sending side and a logic circuit
902
on the receiving side. Logic circuit
901
includes a flip-flop circuit
903
and a driver circuit for signal transfer
904
. Logic circuit
902
includes a transferred signal input circuit
906
and a flip-flop circuit
908
. There is a signal transferring circuit
905
between the logic circuits
901
and
902
.
The logic circuit
901
includes an SCLK driver circuit
910
for sending an output signal SCLK in synchronism with a system clock signal through a transferring circuit SCLK
911
. SCLK transfer circuit
911
is installed in parallel with the signal transferring circuit
905
and a clock signal SCLK exclusively used for transferring is sent to an input circuit SCLK
912
in the logic circuit
902
. The system clock signal (CLK) is supplied from a common clock signal source
909
to the flip-flop circuit
903
, which sends the data signal in synchronism with the system clock signal (CLK). The signal SCLK is supplied to the flip-flop circuit
908
, which receives the data signal in synchronism with the clock signal (SCLK).
FIG. 10
is a timing chart showing the timing of the signals associated with the data transfer according to the clock parallel transfer method employed in FIG.
9
. Signal CLK is the system clock signal, signal Q
1
is an output signal of the flip-flop circuit
903
, signal OUT is an output signal of an output circuit
904
, signal IN is an input signal of an input circuit
906
, signal D
2
is an input signal of the flip-flop circuit
908
, signal Q
2
is an output signal of the circuit
908
and signal SCLK is a clock signal exclusively used for transferring which is supplied to the flip-flop circuit
908
.
In the timing chart using the clock parallel transfer method as shown in
FIG. 10
, the delay time Td from the signal Q
1
to the signal D
2
and the delay value of the delay time Tdck from the system clock signal CLK to the clock signal exclusively used for transferring (SCLK) would be equal as specified in equation (2) because the signal transferring circuit
905
is in parallel with the transferring circuit for SCLK
911
.
Tdck≡Td (2)
According to the clock parallel transfer method employed in
FIG. 9
, even if the delay time used for the circuits
903
,
904
,
906
,
910
and
912
and the delay time used for the circuits
905
and
911
vary based upon deviations in the process of the manufacturing of the respective circuits, equation (2) can be satisfied because the delay time of the respective circuits vary in the same direction. Consequently, the delay time of the circuits
903
,
904
,
905
,
906
,
910
,
911
and
912
can be designed to satisfy equation (2) so as to perform the data transfer between the logic circuits based upon the above method.
SUMMARY OF THE INVENTION
However, in the prior art clock parallel transfer method employed in the arrangement of
FIG. 9
, a problem occurs in that the delay value of the delay time Tdck of the clock signal, used exclusively for transferring, has to be regulated to a fixed cycle in order to achieve a predetermined time difference between a signal sent from the logic circuit on the sending side and a signal reaching the logic circuit on the receiving side, which is within the range of a fixed system clock cycle.
For example, in
FIGS. 9 and 10
, in order to output signal Q
2
three cycles after signal Q
1
is output from the flip-flop circuit
903
, it is necessary to regulate the delay time of the driver circuit
910
, the transferring circuit
911
and the input circuit
912
so that an equation (3) can be satisfied.
2Tck<Tdck≦3Tck (3)
In other words, in the prior art, although it is unnecessary to regulate the delay time between the data signal transfer time and the SCLK transfer time, the delay time Tdck of the parallel transferred clock signal needs to be regulated so that it controls the data transfer to be within a range of t
Saito Tatsuya
Umemura Tetsuya
Yamashita Hiroki
Cao Chun
Hitachi , Ltd.
Lee Thomas C.
Mattingly Stanger & Malur, P.C.
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