Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
1999-12-13
2001-12-11
Meier, Stephen D. (Department: 2822)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S402000, C257S363000
Reexamination Certificate
active
06329691
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to insulated-gate semiconductor devices. More specifically, the present invention relates to a circuit for limiting the maximum voltage applied across the gate dielectric of a semiconductor device.
2. Discussion of Related Art
To produce the fine geometries of modern semiconductor devices, anisotropic dry etching techniques are indispensable. In a typical dry etch (or “plasma etch”) process, an electric field is used to energize an etchant gas into a plasma state. The energized species within the plasma are then directed towards a patterned wafer to perform the etching function. Without this process, sub-2 &mgr;m geometries would be extremely difficult, if not impossible, to produce.
At the same time, the shrinking dimensions of modern semiconductor devices makes such devices more susceptible to damage from stray charge buildup or voltage transients. An insulated-gate, or metal-oxide-semiconductor (MOS) device, such as a transistor or a non-volatile memory (NVM) cell, typically incorporates a very thin gate dielectric layer to improve device performance and reduce power consumption. Unfortunately, radiation effects during plasma etch process steps can threaten the integrity of that thin dielectric layer. The highly energized species created by the plasma can cause a substantial amount of charge to accumulate on metal lines (interconnects) connected to the gate of the MOS device. This charge buildup then produces a large voltage potential across the gate dielectric. A voltage in excess of a limit voltage (specific to the particular device) can render the MOS device unusable by physically degrading the gate dielectric, or by causing electrons to tunnel into the gate dielectric and shift the device threshold voltage.
To guard against these damaging effects, a diode is typically connected in parallel with any sensitive gates. The diode is intended to limit the maximum voltage that can build up across the gate dielectric, while not interfering with normal operating voltages.
FIG. 1
depicts a conventional protective scheme, showing a planar diode
120
coupled to a MOS device
110
in an integrated circuit (IC) (not shown). Device
110
comprises an n+ region drain
116
and an n+ region source
118
, both of which are formed in a p-type substrate
190
. MOS device
110
further comprises a control gate
112
and a gate dielectric
114
. Gate dielectric
114
can comprise various layers depending on the application of MOS device
110
. For example, a NVM cell might include a gate dielectric comprising a “stack” of oxide and nitride layers, whereas a standard MOS transistor would have just a single oxide layer. Regardless of its particular structure, however, gate dielectric
114
would require protection from excessive charge buildup at control gate
112
.
Diode
120
performs that protective function for gate dielectric
114
. Diode
120
comprises an n+ region
122
formed in a p-well
124
. The resulting p-n junction provides the protective diode action of circuit
120
, with n+ region
122
serving as a cathode and p-well
124
serving as an anode. N+ region
122
is connected to gate
112
of MOS device
110
by an interconnect
102
. Because substrate
190
serves as a “bulk ground” (common ground) for all devices in the IC, diode
120
is effectively coupled in parallel with gate dielectric
114
of MOS device
110
.
FIG. 2
shows a circuit electrically equivalent to the structure in FIG.
1
.
FIG. 2
shows a diode
220
cathode-coupled to the gate (control) terminal of a MOS device
210
in an integrated circuit (IC) (not shown). The anode of diode
220
and the body terminal of MOS device
210
are both coupled to bulk ground of the IC. The power terminals of MOS device
210
are coupled to various other devices (not shown) within the IC.
The gate terminal of MOS device
210
is coupled to receive an input (control) voltage Vin. During normal operation of the IC, voltage Vin switches between several predetermined control voltages. Those control voltages are sized so as not cause any damage to MOS device
210
. However, prior to actual use, the gate terminal of MOS device
210
is typically “floating”, i.e., not coupled to any voltage source. Therefore, during manufacturing, voltage Vin is not regulated, and the magnitude of voltage Vin is determined by whatever charge accumulates on interconnects coupled to the gate terminal of MOS device
210
. This type of “induced” voltage Vin can have a magnitude far in excess of normal control voltages. This is especially true during plasma etch processes, which can generate an effective voltage Vin of more than 15V. This is much higher than the damage threshold of most modern semiconductor devices. For example, a typical non-volatile memory (NVM) cell, such as described in U.S. Pat. No. 5,768,192, has a gate dielectric thickness of less than 200A. As the voltage across the gate dielectric of such a device rises above 12.5V, charge can start to tunnel into the dielectric. This in turn can shift the threshold voltage of the device and render it unusable.
Diode
220
protects MOS device
210
from any potentially damaging positive gate voltages. When charge buildup raises voltage Vin to the reverse breakdown voltage Vb of diode
220
, diode
220
goes into reverse conduction, draining away any additional charge. Diode
220
sets an upper limit on input voltage Vin, ensuring that the actual gate voltage seen by MOS device
210
can never rise above voltage Vb. At the same time, normal positive control voltages are not affected by diode
220
. When a positive control voltage is applied to the gate terminal of MOS device
210
, diode
220
is reverse biased and does not conduct. Therefore, proper protective function is achieved by sizing diode
220
such that its reverse breakdown voltage Vb is: a) greater than any control voltage to be applied to the gate terminal of MOS device
210
; and b) below a “limit voltage” at which the gate dielectric of MOS device
210
would begin to be affected.
However, many modern devices require that input voltage Vin vary between both positive and negative voltages; for instance to program and erase certain types of NVM cells. In such cases, the conventional single-diode scheme shown in
FIG. 2
is problematic. When voltage Vin is negative, diode
220
goes into forward conduction, shunting the gate and body terminals of MOS device
210
. The magnitude of the gate voltage seen by MOS device
210
is then limited to the forward voltage drop Vf of diode
220
. Typically, the forward voltage drop of a diode is quite small. The negative voltage at the gate terminal of MOS device
210
is therefore prevented from reaching the level required for proper device operation.
For example, assume MOS device
210
is coupled to receive input voltages Vin of +9V and −9V during normal operation, and that any gate voltage over +12.5V would damage the gate dielectric of MOS device
210
. Also, assume that plasma etch steps during the manufacturing process can generate input voltages of up to +15V. Finally, assume diode
220
has a forward voltage drop Vf of 0.6V and a reverse breakdown voltage Vb of 11.5V, typical values for a planar diode formed in a semiconductor substrate. During manufacturing, diode
220
limits the gate voltage of MOS device
210
to a “safe” +11.5V, even if charge buildup on the gate tries to pull the voltage to +15V. During normal operation, when input voltage Vin is at +9V, diode
220
is reversed biased, so the gate voltage is unaffected at +9 v. However, when input voltage Vin swings to −9V, diode
220
is forward biased and begins to conduct. The actual gate voltage seen by MOS device
210
is only −0.6V, not enough to properly operate transistor
210
. As a result, the conventional single-diode protection circuit shown in
FIG. 2
is inappropriate for devices requiring negative control voltages during normal operation. The results are
Bever Hoffman & Harms LLP
Hoffman E. Eric
Kubodera John M.
Meier Stephen D.
Tower Semiconductor Ltd.
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