Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
2000-12-20
2002-05-21
Wilson, Allan R. (Department: 2815)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S355000
Reexamination Certificate
active
06392276
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to the protection of structures of silicon-on-insulator type (SOI), including cells having their bottoms and walls insulated by a dielectric material and in which different elementary components or groups of components are arranged. The protection of such cells against electrostatic discharges, capable of causing deterioration of the cells due to voltage breakdown, will more specifically be considered.
2. Discussion of the Related Art
SOI technologies are currently mainly used in the fields of low and medium voltage integrated circuits, that is, circuits intended for withstanding at most voltages on the order of some ten volts. In such integrated circuits, as the basic components become smaller and smaller, they become more and more sensitive to electrostatic discharges. Thus, conventionally, a system of protection against electrostatic discharges is often provided on all inputs/outputs of the various integrated circuit cells.
A specific problem arises in the case where an SOI technology is used to form circuits including high-power components, to which a high voltage is likely to be applied. In this case, in normal operation, differences of several hundreds of volts may be found between two neighboring cells. These cells must then be protected and the protection circuit must be calibrated so as not to be triggered in normal operation of the device but for being triggered before the high voltages exceed a predetermined threshold.
SUMMARY OF THE INVENTION
The present invention more specifically aims at solving the problem of protecting the oxides between cells or at the bottom of cells in the case where the structure includes cells that normally have to withstand high voltages.
To achieve this and other objects, the present invention provides a device for protecting a structure of SOI type including several insulated cells, each cell being formed of a portion of a semiconductor substrate of a first conductivity type having its bottom and its lateral walls delimited by an insulating area, including a protective cell that includes a first semiconductor region of the second conductivity type connected to a reference potential and several second regions of the second conductivity type separated from one another and from the first region, the substrate portion of each of the cells other than the protective cell being connected to one of the second regions.
According to an embodiment of the present invention, the bottom and the walls of each of the cells include a peripheral region of the first conductivity type of high doping level.
According to an embodiment of the present invention, the connection of each cell to the protective cell includes a region of the first conductivity type of high doping level, continuous with said peripheral doping region.
According to an embodiment of the present invention, the rear surface layer of the SOI structure is also connected to one of the second regions.
REFERENCES:
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patent: 5767562 (1998-06-01), Yamashita et al.
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patent: 6060752 (2000-05-01), Williams
patent: A-0 923 132 (1999-06-01), None
Ohtomo Y et al, “A Quarter-Micron Simox-CMOS I VTTI-Compatible Gate Array With An Over 2,000 V ESD-Protection Circuit”, Proccedings of The IEEE CUstom Integrated Circuits Conference (CICC), US, New York, vol. Conf 18, 1996, pp. 57-60.
Morris James H.
STMicroelectronics S.A.
Wilson Allan R.
Wolf Greenfield & Sacks P.C.
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