Device for protecting a programmable non-volatile memory

Details Device for protecting a programmable non-volatile memory Device for protecting a programmable non-volatile memory

1999-11-23

2001-09-18

Tokar, Michael (Department: 2819)

Electronic digital logic circuitry

Security

C326S037000, C711S163000

Reexamination Certificate

active

06292012

ABSTRACT:

CROSS-REFERENCE TO RELATED APPLICATION
This application claims the priority benefit of Taiwan application serial no. 88117221, filed Oct. 06, 1999.
BACKGROUND OF THE INVENTION
1. Field of Invention
The present invention relates to a mechanism that controls the reprogramming of memory. More particularly, the present invention relates to a device capable of preventing the loss of data from programmable non-volatile memory due to illegally tampering or reprogramming.
2. Description of Related Art
To satisfy the need for plug and play function, the basic input/output system (BIOS) program for starting a personal computer (PC) is stored inside a programmable non-volatile memory. In fact, programmable non-volatile memory such as electrical erasable programmable read only memory (EEPROM) or flash ROM is used as a storage medium because stored data can be retained after power is cut off. New data can still be written into the memory, if necessary, however, due to the re-programmable capability, the BIOS program is an easy target for corruption through a computer virus attack. Once data within the BIOS program is erased or changed, the computer can start only with difficulty. The cost of recovering from the damage caused by a virus attack is usually very high. Moreover, data within the BIOS is very much dependent upon the type of computer. Hence, a universal solution to the problem is difficult to find.
FIG. 1
is a block diagram showing a conventional re-programming control mechanism for a flash ROM. In fact, most programmable non-volatile memory also employs the same type of re-programming mechanism. In
FIG. 1
, the flash memory
10
includes a combinatorial logic circuit
12
and a flash memory cell array
14
. Lines having the labels I
0l
-I
0n
represent the input signal to the combinatorial logic circuit
12
. These are the memory write enable signals. In other words, these are the internal signals for reprogramming control.
When the input signals I
0l
-I
0n
picked up by the combinatorial logic circuit
12
match a set of internal parameters, the combinatorial logic circuit
12
issues a logic ‘true’ output signal on the memory write enable MWE line. Conversely, if the input signals I
0l
-I
0n
picked up by the combinatorial logic circuit
12
do not match the set of internal parameters, a logic ‘false’ signal is issued on the memory write enable MWE line. As soon as the flash memory cell array
14
receives a logic ‘true’ signal from the memory write enable MWE line, the flash memory cell array
14
can be re-programmed. However, if the flash memory cell array
14
receives a logic ‘false’ signal from the MWE line, re-programming of the flash memory cell array
14
is not allowed. In the above description, a logic ‘true’ may mean either a high potential ‘1’ or a low potential ‘0’ depending on the design.
With the aforementioned circuit arrangement, any software programmer knowing the set of internal parameters of the combinatorial logic circuit
12
can re-program the flash memory cell array
14
in whatever ways desired. Consequently, corruption of the BIOS program inside the memory is possible.
SUMMARY OF THE INVENTION
The present invention provides a device capable of preventing the loss of data from programmable non-volatile memory due to illegal tampering or reprogramming.
To achieve these and other advantages and in accordance with the purpose of the invention, as embodied and broadly described herein, the invention provides a device capable of protecting the pro gram data inside a programmable non-volatile memory. The device includes a first and a second combinatorial logic circuit, a delay circuit, a low-enable latching device with reset capability, an AND gate and a memory cell array. In the device of the invention, when all the necessary system startup operations dictated by the BIOS program inside the memory cell array are executed and a specified memory read/write program that matches the preset internal parameters of a logic circuit is activated, the memory cell array is permanently locked in a non-programmable state unless the power of the device is turned off and then restarted. There is no way for any software program to change the programming state of the memory cell array back to a re-programming state again. Hence, the device is an effective means of protecting the programs inside the memory from illegal tampering.
In the device of the invention, the input terminals of the first combinatorial logic circuit receives a first set of input signals while the input terminals of the second combinatorial logic circuit receives a second set of input signals. The output terminal of the first combinatorial logic circuit are used for issuing a memory write enable signal, whereas the output terminal of the second combinatorial logic circuit are used for issuing a reset signal. The input terminal of the delay circuit is coupled to a source voltage while the output terminal is used for issuing an enable signal. The input terminals of the low-enable latching device is coupled to a source voltage and the output terminal of the delay circuit, respectively. The control terminal of the low-enable latching device is coupled to the output terminal of the second combinatorial logic circuit. The output terminal of the low-enable latching device issues an output signal. The input terminals of the AND gate are coupled to the output terminal of the first combinatorial logic circuit and the output terminal of the low-enable latching device, respectively. The output terminal of the AND gate issues a memory re-program control signal. The memory cell array is a device for storing programs or data. The memory cell array is coupled to the output terminal of the AND gate. In operation, when the first and the second set of input signals sent to the first and the second combinatorial logic circuit both match their respective preset internal parameters, the first and the second combinatorial logic circuit send out a logic ‘true’ signal on the memory write enable line and the reset line, respectively. On the other hand, when the first and the second set of input signals sent to the first and the second combinatorial logic circuit do not match their respective preset internal parameters, the first and the second combinatorial logic circuit send out a logic ‘false’ signal on the memory write enable line and the reset line, respectively. As long as the memory re-program control signal receives a logic ‘false’ signal, nothing can be programmed into the memory cell array. In contrast, if the memory re-program control signal receives a logic ‘true’ signal, re-programming of the memory cell array is allowed. The invention dictates that as long as the BIOS program within the memory cell array is executed and specified memory read/write procedures for matching the preset internal parameters of the second combinatorial logic circuit are activated so that a logic ‘false’ signal is issued from the output terminal of the AND gate, the memory cell array is locked up in a non-re-programmable state unless the power is turned off and then restarted. Once in the non-programmable state, software programs can no longer change the non-programming status and tamper with the original program code. Hence, illegal re-programming is prevented.
It is to be understood that both the foregoing general description and the following detailed description are exemplary, and are intended to provide further explanation of the invention as claimed.


REFERENCES:
patent: 5119336 (1992-06-01), Itoh
patent: 5721872 (1998-02-01), Katsuta
patent: 363310214A (1988-12-01), None

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