Error detection/correction and fault detection/recovery – Pulse or data error handling – Memory testing
Reexamination Certificate
2005-03-22
2005-03-22
Lamarre, Guy J. (Department: 2133)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Memory testing
C365S185090
Reexamination Certificate
active
06871305
ABSTRACT:
A device for prolonging the lifetime of a nonvolatile memory is applied to the connection between a host electronic machine and a nonvolatile memory device. The device includes a RAM (Random Access Memory) buffer zone, a counter, and two sets of inverters, wherein the RAM buffer zone is employed to store a unit data train temporarily; the counter is used to count the total bits of logic “0”; the inverters are used to lessen the times for readying/writing a nonvolatile memory device by inverting the unit data train based on the count (for example, when the number of logic “1“s exceeds the number of logic “0“s, and the state flag keeps track of whether an inversion has occurred or is needed.
REFERENCES:
patent: 5561632 (1996-10-01), Arase et al.
patent: 5930169 (1999-07-01), Iwata et al.
patent: 6160739 (2000-12-01), Wong
Chang Wen-Chung
Chien Cheng-Chih
Fu Jou-Wei
Wu Bing-Fei
Bacon & Thomas PLLC
Britt Cynthia
Lamarre Guy J.
Silicon Motion Inc.
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