Pulse or digital communications – Synchronizers – Phase displacement – slip or jitter correction
Patent
1994-10-18
1997-04-15
Chin, Stephen
Pulse or digital communications
Synchronizers
Phase displacement, slip or jitter correction
370516, H04L 700
Patent
active
056217757
ABSTRACT:
A digital bit stream from a first synchronous link is timed by a first clock and is to be sent over a second synchronous link timed by a second clock. A device for justifying the bit stream at regular intervals includes a buffer memory. Respective pointers supply buffer memory write and read addresses. A value indicating how full the buffer memory is is calculated and compared to first and second threshold values to produce a justification command signal. The first and second variable threshold values are determined according to the phase difference between the header of a row received from the first link and the header of a row sent at the same time on the second link. The device finds an application in gateways at the input of and in telecommunication networks using the synchronous digital hierarchy.
REFERENCES:
patent: 4791652 (1988-12-01), McEachern et al.
patent: 5331641 (1994-07-01), Parruck et al.
patent: 5459782 (1995-10-01), Volejnik
patent: 5471476 (1995-11-01), Hiramoto
Ralp Urbansky "Simulation Results and Field Trial Experience of Justification Jitter", World Telecommunications Forum Tech. Symp., No. 2, Oct. 10, 1991, pp. 45-49 French Search Report FR 9312497.
Alcatel Cit
Chin Stephen
Le Amanda T.
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