Static information storage and retrieval – Read/write circuit
Patent
1993-11-03
1995-05-02
Fears, Terrell W.
Static information storage and retrieval
Read/write circuit
36523001, 365226, G11C 1300
Patent
active
054126029
DESCRIPTION:
BRIEF SUMMARY
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a device for generating a voltage for programming a programmable permanent memory, especially a memory of EPROM type.
It also concerns a method implemented in this device as well as a memory incorporating this device.
2. Discussion of the Related Art
During operations for programming programmable memories, especially of EPROM type, the voltage generators with which these memories are endowed must deliver, from an external applied voltage, a stabilized programming voltage to memory cells which represent an equivalent load of substantially variable impedance. Now, present-day generating devices generally have too high an output impedance to contribute to limiting to reasonable levels the programming voltage variations induced by the constraints inherent in manufacture.
Now, excessive voltage variations give rise to constraints on the components which may lead to their degradation and destruction.
An object of the present invention is to remedy these disadvantages by providing a device for generating a voltage for programming a programmable permanent memory, especially of EPROM type, from an external DC voltage source, comprising means for generating a reference voltage.
SUMMARY OF THE INVENTION
According to the invention, this device comprises means for duplicating said reference voltage, arranged as a current and voltage mirror structure and generating the programming voltage as output, and a follower MOS transistor whose drain and source are connected respectively to the external DC voltage source and to the output of said duplicating means and whose gate is connected to a predetermined internal node of said means for generating a reference voltage.
Thus, with the device according to the invention, there is available a programming voltage delivered by a generator having an output impedance which is considerably reduced with respect to the prior-art devices through recourse to duplicating means employing a mirror structure. A negative feedback loop produced by the link between the gate of the follower transistor and the reference generating means, furthermore contributes to stabilizing the programming voltage. In practice, this loop has a high negative gain with respect to the variations in the output voltage. This affords self-adaptation of the device according to the invention to variable conditions of load current.
According to an advantageous version of the invention, the means for generating a reference voltage comprise a first MOS transistor whose source is connected to the external DC voltage source and a second MOS transistor whose drain is connected to earth, a first, a second and a third resistive element connected in series between the external DC voltage source and earth, the gate of the first MOS transistor being connected to a junction node between the first and second resistive elements whilst the gate of the second MOS transistor is connected to a junction node between the second and third resistive elements, and the duplicating means comprise a first mirror MOS transistor whose drain and source are connected respectively to the drain of the first MOS transistor and to the source of the second MOS transistor of said means for generating a reference voltage.
According to a preferred embodiment of the invention, the duplicating means furthermore comprise a second mirror MOS transistor whose gate is connected to the gate of the first mirror MOS transistor and whose source constitutes the output of said duplicating means, and a third mirror MOS transistor whose gate, source and drain are connected respectively to the gate of the first MOS transistor of the generating means, to the external DC voltage source and to the drain of the second mirror MOS transistor.
According to another aspect of the invention, the method of generating a voltage for programming a programmable permanent memory, especially of EPROM type, from an external DC voltage source, comprises a first step for generating a reference voltage
REFERENCES:
Microprocessors and Microsystems, vol. 14, No. 8, Oct. 1990, London, GB, pp. 543-549, Zales S. et al, "Intel Flash EPROM for In-System Reprogrammable Nonvolatile Storage".
IEEE Journal of Solid-State Circuits, vol. SC-22, No. 4, Aug. 1987, New York, US, pp. 548-552, Masouka F. et al, "A 256-Kbit Flash EEPROM Using Triple-Polysilicon Technology".
Fears Terrell W.
SGS-Thomson Microelectronics S.A.
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