Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2007-02-20
2007-02-20
Chiang, Jack (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
Reexamination Certificate
active
10879768
ABSTRACT:
A method and computer program for estimating a cell delay for an integrated circuit design include steps of selecting a range of values for cell ramptime and load and a range of values for an additional cell parameter. The values for cell ramptime, load, and the additional cell parameter are arranged in a lookup table. A cell delay is calculated for each combination of cell ramptime, load, and the additional cell parameter for the lookup table.
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McGonagle Timothy
Shusta Gregory
Wright Brad
Chiang Jack
LSI Logic Corporation
Parihar Suchin
Whitesell Eric James
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