Device for estimating a timing correction loop error for a...

Details Device for estimating a timing correction loop error for a... Device for estimating a timing correction loop error for a...

2005-11-09

2010-02-09

Liu, Shuwang (Department: 2611)

Pulse or digital communications

Synchronizers

Synchronizing the sampling time of digital data

C375S373000, C375S320000, C375S329000, C370S503000, C370S516000

Reexamination Certificate

active

07660377

ABSTRACT:
A device for providing a digital error signal, for a timing correction loop of a digital demodulator for digital transmission by phase modulation or amplitude and phase modulation, the device successively receiving pairs of digital signals representative of the components of complex signals, and having circuitry for providing a difference signal representative of the difference between the modulus of the complex signal corresponding to the last received pair of digital signals and the modulus of the complex signal corresponding to the previously-received pair of digital signals; circuitry for providing a weighting factor which depends on the angle between the complex signal corresponding to the last received pair of digital signals and the complex signal corresponding to the previously-received pair of digital signals; and circuitry for providing the error signal proportional to the product of the difference signal and of the weighting factor.

REFERENCES:
patent: 4416015 (1983-11-01), Gitlin
patent: 4646173 (1987-02-01), Kammeyer et al.
patent: 6377634 (2002-04-01), Yamamoto
patent: 6621857 (2003-09-01), Belotserkovsky et al.
patent: 2001/0017902 (2001-08-01), Yamagata et al.
patent: 2001/0031021 (2001-10-01), Fujimura et al.
patent: 2001/0048723 (2001-12-01), Oh
French Search Report from French Patent Application 04/52576, filed Nov. 9, 2004.

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