Electrical computers and digital data processing systems: input/ – Interrupt processing – Processor status
Reexamination Certificate
1997-06-11
2001-01-16
De Cady, Albert (Department: 2784)
Electrical computers and digital data processing systems: input/
Interrupt processing
Processor status
C712S244000, C712S040000
Reexamination Certificate
active
06175890
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention generally relates to a microprocessor capable of an interrupt process and an adaptor device coupled to such a microprocessor, and more particularly, to a microprocessor and an adaptor device efficiently handling interrupt request processes.
2. Description of the Related Art
In a system where a microprocessor is connected to a plurality of external devices, a plurality of interrupt requests for accessing the microprocessor may occur simultaneously. These requests may or may not be accepted depending on how the microprocessor is executing a current process.
Acceptance of requests is controlled by an interruption mask flag (hereinafter, simply referred to as a mask flag) set in a mask register usually provided in the microprocessor. For example, an interruption is enabled when the mask flag is set to 0 and is disabled when the mask flag is set to 1. Hereinafter, a “mask level state” will refer to a status of a microprocessor process characterized by a unique set of mask flags.
The number of mask flags available depends on the architecture of the microprocessor. If the number of interrupt requests exceeds the number of the mask flags, it is impossible to enable or disable interrupt requests on an independent basis.
A first conceivable approach to resolve this disadvantage is to increase the number of mask registers. If such an approach is introduced in a system where relatively few interrupt requests occur, many of the registers provided may seldom be necessary. It is also to be noted that mask flags should essentially be saved before the control is turned to an interrupt process because otherwise it is impossible to return to an original mask level state after an interrupt process is completed. According to the first conceivable approach, it is necessary to save the content of a large number of mask registers to a stack when an interrupt request is acknowledged and restore the saved mask register contents when the control is returned to a normal process from the interrupt process. Thus, if a system does not require a large number of mask flags, the first conceivable approach would prove disadvantageous since it slows down the interrupt process and causes a large portion of the memory allocated to the stack to be consumed.
In an alternative approach, mask flags could be provided outside the microprocessor. More specifically, mask flags may be provided in a register of an adaptor device coupled to the microprocessor when the internal registers of the microprocessor can no longer accommodate a satisfactory number of mask flags or mask levels. For example, Japanese Laid-Open Patent Application No. 4-51329 discloses a technology where the content (context) of a register built into a coprocessor (an adaptor device) preceding the interruption is compared to that subsequent to the interruption, whereupon the context of the coprocessor is saved to a stack only when it is found that the CPU is assigned to a task requiring the use of the coprocessor. In this approach, the CPU reads the context from the coprocessor and writes the same to the stack. In other words, the CPU performs a stack write operation.
If an adaptor device external to the microprocessor is provided with a mask register, saving of that mask register content in an event of an interruption and restoring of the mask register content upon a return from the interrupt process are executed by software (interrupt process program) according to the related art.
Therefore, any approach whereby mask flags are merely provided in an adaptor device has a disadvantage in that the processing time increases. This disadvantage is particularly noticeable in a system in which multiple interruptions are enabled. In such a system, a second interrupt request occurring subsequent to a first interrupt request has to wait until the first interrupt request is accepted and the mask register content is saved. Since it takes time for software to save the mask register content upon the acceptance of the first interrupt request, the second interrupt request has to wait a certain period of time before it is accepted.
A conceivable approach whereby the mask register content is saved in hardware outside the microprocessor requires the use of relatively large-scale hardware including an address generating circuit for generating an address at which the mask register content is saved. Therefore, such an approach tends to increase the cost of a system involving the microprocessor.
SUMMARY OF THE INVENTION
Accordingly, a general object of the present invention is to provide a microprocessor and an adaptor device in which the aforementioned disadvantages are eliminated.
Another and more specific object of the present invention is to provide a microprocessor and an adaptor device in which data provided in the adaptor device is efficiently saved to a stack in an interrupt process and the data thus saved is efficiently restored when the control is returned to a normal process.
The aforementioned objects of the present invention can be achieved by a microprocessor capable of interrupt process, comprising: input means for receiving a signal requesting a unique write bus cycle in which the microprocessor does not provide data to a data bus connected to the microprocessor; saving means for saving a program counter content and a processor status register content to a stack; and write bus cycle generating means for generating, when an interrupt request occurs and when the input means receives the signal, the unique write bus cycle for writing to the stack, by putting the data bus to a high-impedance status and by introducing a unique bus status different from a bus status in which a normal program-driven stack write from the microprocessor to a memory occurs.
According to the microprocessor of the present invention, data provided in the adaptor device is efficiently saved in an interrupt process to a stack provided in a memory.
The aforementioned objects could also be achieved by a microprocessor capable of interrupt process comprising: input means for receiving a signal requesting a unique read bus cycle in which the microprocessor neglects data on a data bus connected to the microprocessor; read bus cycle generating means for generating a normal read bus cycle in which a normal stack read from a memory to the microprocessor occurs, and for generating, in accordance with an interrupt process program, the unique read bus cycle for reading from a stack, by introducing a unique bus status different from a bus status in which a normal stack read from a memory to the microprocessor occurs; and returning means for returning from the interrupt process program by restoring a program counter and a processor status register on the normal read bus cycle.
According to this aspect of the invention, data in the adaptor device coupled to the microprocessor is efficiently restored from a stack when the control is returned from an interrupt process to a normal process.
The aforementioned objects could also be achieved by an adaptor device connected to a microprocessor via a data bus, the microprocessor comprising: input means for receiving a signal requesting a unique write bus cycle in which the microprocessor does not provide data to the data bus connected to the microprocessor and a unique read bus cycle in which the microprocessor neglects data on a data bus connected to the microprocessor; saving means for saving a program counter content and a processor status register content to a stack; write bus cycle generating means for generating, when an interrupt request occurs and when the input means receives the signal, the unique bus cycle for writing to the stack, by putting the data bus to a high-impedance status and by introducing a unique bus status different from a status in which a normal program-driven stack write from the microprocessor to a memory occurs; read bus cycle generating means for generating a normal read bus cycle in which a normal stack read from a memory to the microprocessor occurs, and fo
Abraham Esaw
Cady Albert De
Cooper & Dunham LLP
Ricoh & Company, Ltd.
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