Static information storage and retrieval – Read/write circuit – Signals
Reexamination Certificate
1999-02-04
2001-05-15
Tran, Andrew Q. (Department: 2824)
Static information storage and retrieval
Read/write circuit
Signals
C365S194000, C365S193000, C365S210130, C365S189070
Reexamination Certificate
active
06233180
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to methods and devices for timing data retrieval in semiconductor memory systems, in general, and to methods and devices for determining the validity of word-line conditions, in particular.
BACKGROUND OF THE INVENTION
Memory devices, such as random access memory (RAM), read only memory (ROM), non-volatile memory (NVM) and the like, are known in the art. A memory device includes an array of memory cells and peripheral supporting systems for managing programming and data retrieval operations.
Reference is now made to
FIG. 1
, which is a schematic illustration of a memory device, generally referenced
10
, which is known in the art.
Device
10
includes a plurality of memory cells, generally referenced
16
, an X-decoder
20
, a Y-decoder
26
, a delay unit
22
, and a sensing amplifier
24
.
The memory cells
16
are arranged in an array, in the form of an N×M matrix. Access to the cells is performed via a plurality of bit lines, generally referenced
14
, and a plurality of word-lines, generally referenced
12
. Each memory cell
16
is connected to one word-line
12
and between two neighboring bit lines
14
.
For example, all of the cells in the left column, such as cells
16
(1,1)
and
16
(1,K)
, are connected between bit-lines
14
1
and
14
2
. Cells
16
which are located in the same row are connected to the same word-line
12
. For example, all of the cells
16
in the Kth line, such as cells
16
(1,K)
,
16
(L,K)
,
16
(L+1,K)
and
16
(L+2,K)
, are connected to word-line
12
K
.
A cell
16
can be accessed by providing predetermined voltage levels to the word-line
12
and the bit-lines
14
which are connected thereto. The gate of the cell receives a predetermined voltage level signal via the respective word-line
12
, and the source and drain of the cell receive different voltage level signals, each from its respective bit-line
14
.
The bit-lines
14
are selected using Y-decoder
26
, which connects them to voltage sources (not shown) and to sensing amplifier
24
. A word-line
12
is selected using the X-decoder
20
which includes an address decoder
21
and a plurality of word-line drivers
23
, each activating a specific word-line
12
when so indicated by the address decoder
21
.
It is noted that the selection process of X-decoder
20
takes a considerable period of time, particularly due to the operations of the address decoder
21
. This time period varies according to a plurality of aspects, such as the length of the path to the selected word-line
12
, the environmental conditions (voltage supply, temperature, manufacturing process), and the like.
The sensing amplifier
24
should begin the sensing procedure only after the gate voltage provided to the selected word-line
12
reaches a predetermined threshold level. To ensure this, the memory device includes a delay unit
22
which provides a control signal &PHgr;
2
to sensing amplifier
24
. When control signal &PHgr;
2
indicates that the word-line voltage has exceeded the predetermined threshold level, sensing amplifier
24
commences the sensing procedure.
Methods for determining the length of delay which delay unit
22
implements (i.e., the period from the time that the X-decoder
20
receives a command to select a specific word-line until the time that the voltage on that specific word-line exceeds the threshold level) are known in the art.
One of these methods includes detecting the actual voltage on the selected word-line. As such, a reference word-line is fed directly into delay unit
22
. Typically the reference word-line is a specific word-line, such as word-line
12
K
. Hence, the actual voltage from the specific word-line itself is detected, thus avoiding the task of determining the voltage level.
However, this method is very complex and hard to implement, since it requires tapping directly to the selected word-line and detecting the voltage level thereon. Furthermore, in order to implement this method, each word-line in the array must be hooked up to a switch and a comparator, a solution which requires large chip area.
In another method, the reference-word line fed into the delay unit is a DC reference line. In such an instance, the DC reference line is connected to a capacitor and a resistor, thus providing a built-in delay signal. This method however, gives a signal without any matching to the word-line.
Yet another method includes determining the delay by fixed predetermined delay calculations which take into consideration the structure of the X-decoder
20
, the memory circuit, the range of the V
CC
voltage levels which are provided to the device, and the like.
Reference is further made to
FIGS. 2A and 2B
, which are timing diagrams known in the art.
FIG. 2A
illustrates a conventional address signal, generally referenced
50
, and
FIG. 2B
illustrates control signal &PHgr;
2
.
Upon receipt of address signal
50
, both delay unit
22
and address decoder
21
begin operation. Delay unit
22
initially causes control signal &PHgr;
2
to descend, thereby deactivating sensing amplifier
24
, after which delay unit
22
waits a predetermined delay, generally referenced
62
. Meanwhile, the address decoder
21
decodes the address and activates the relevant word-line driver
23
to provide voltage to the selected word-line
12
. At the end of predetermined delay
62
, which is longer than the expected time required for the selected word-line
12
to reach or exceed the predetermined threshold level, delay unit
22
causes control signal &PHgr;
2
to rise, thereby activating sensing amplifier
24
.
It is noted that it is often very difficult to accurately determine the point at which the word-line voltage exceeds the predetermined threshold, since this level is subject to change according to a plurality of factors.
To overcome this phenomena, the delay time period is often set much longer than necessary so as to comply with the worst case which might occur. In such an instance, since the delay time period is prolonged, it is possible to by-pass sensing amplifier
24
entirely, and thus, delay unit
22
connects directly to Y-decoder
26
. In such an example, delay unit
22
directly actives the Y decoder
26
. It will be appreciated by those skilled in the art that by doing so, a considerable amount of time is wasted and the device operates much slower than desired.
SUMMARY OF THE PRESENT INVENTION
It is an object of the present invention to provide a dynamically determined delay.
There is therefore provided in accordance with a preferred embodiment of the present invention, a delay device for delaying the activation of a sensing indication signal. The delay device includes a reference word-line, a reference word-line driver and a comparator.
The reference word-line driver is connected to the reference word-line and a power supply, and is controlled by a strobe signal. Additionally, when so indicated by the strobe signal, the reference word-line driver provides a power supply voltage to the reference word-line.
The comparator is connected to the reference word-line and to the power supply, and activates the sensing indication signal when the voltage on the reference word-line is at least equal to a predetermined function of the power supply voltage.
In a preferred embodiment, the reference word-line includes a word-line or a portion of a word-line.
The comparator includes a controller for supplying power to the comparator during an active mode of an array, and for not supplying power during a standby mode of the array.
There is therefore provided in accordance with a preferred embodiment of the present invention, a delay device for determining a data sensing delay. The delay device includes a reference word-line, and a comparator connected to the reference word-line and to a power supply. When the voltage on the reference word-line is at least equal to a predetermined function of the power supply voltage, the comparator activates a sensing signal.
There is therefore additionally provided in accordance with a preferred
Dadashev Oleg
Eitan Boaz
Saifun Semiconductors Ltd.
Tran Andrew Q.
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