Device for blocking bus transactions during reset

Details Device for blocking bus transactions during reset Device for blocking bus transactions during reset

1998-04-07

2000-08-22

Palys, Joseph E.

Electrical computers and digital processing systems: support

Digital data processing system initialization or configuration

713400, 710106, G06F 15177, G06F 112, G06F 1342

Patent

active

061087785

ABSTRACT:
The present invention comprises a host bus clocked in a host clock domain, a secondary bus for receiving a reset command clocked in a secondary bus clock domain and a controller for dynamically delaying transactions on the host bus until the secondary bus is out of reset.

REFERENCES:
patent: 5377325 (1994-12-01), Chan
patent: 5434996 (1995-07-01), Bell
patent: 5524237 (1996-06-01), Bestler
patent: 5654988 (1997-08-01), Heyward
patent: 5758170 (1998-05-01), Woodward
patent: 5832241 (1998-11-01), Guy
patent: 5923858 (1999-07-01), Kanekal

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