Electrical computers and digital data processing systems: input/ – Access arbitrating – Centralized arbitrating
Reexamination Certificate
2006-03-17
2011-12-27
Zaman, Faisal M (Department: 2111)
Electrical computers and digital data processing systems: input/
Access arbitrating
Centralized arbitrating
C710S057000, C710S240000, C710S244000
Reexamination Certificate
active
08086776
ABSTRACT:
In an information-processing apparatus including a plurality of modules and a first arbiter which arbitrates bus-access requests of the plurality of modules, at least one of the plurality of modules includes a plurality of submodules and a second arbiter which arbitrates bus-access requests of the plurality of submodules and transmits at least one of the bus-access requests of the plurality of submodules to the first arbiter. The first arbiter gives priority to the module which transmits many bus-access requests, or the module which made a previous bus access, and limits the number of consecutive accesses made by the same module, so as to control the priority of accessing the bus by the plurality of modules. The second arbiter controls priority of accessing the bus by the plurality of submodules according to the free state of a buffer of each submodule, or the access type, whereby the bus-access requests made by the plurality of modules can be arbitrated, thus increasing bus-use efficiency.
REFERENCES:
patent: 4161779 (1979-07-01), Spencer et al.
patent: 4191997 (1980-03-01), Luiz
patent: 4761807 (1988-08-01), Matthews et al.
patent: 4922244 (1990-05-01), Hullett et al.
patent: 4924380 (1990-05-01), McKinney et al.
patent: 5025370 (1991-06-01), Koegel et al.
patent: 5414666 (1995-05-01), Kumagai et al.
patent: 5444855 (1995-08-01), Thompson
patent: 5561823 (1996-10-01), Anderson
patent: 5581782 (1996-12-01), Sarangdhar et al.
patent: 5649157 (1997-07-01), Williams
patent: 5666494 (1997-09-01), Mote, Jr.
patent: 5860110 (1999-01-01), Fukui et al.
patent: 5996037 (1999-11-01), Emnett
patent: 6014722 (2000-01-01), Rudin et al.
patent: 6189061 (2001-02-01), Katz et al.
patent: 6385671 (2002-05-01), Hunsaker et al.
patent: 6418148 (2002-07-01), Kumar et al.
patent: 6460095 (2002-10-01), Ueno et al.
patent: 6629220 (2003-09-01), Dyer
patent: 6804736 (2004-10-01), Olarig
patent: 6836812 (2004-12-01), Lin
patent: 6839784 (2005-01-01), Ennis et al.
patent: 7080177 (2006-07-01), Neuman
patent: 7099972 (2006-08-01), Chao
patent: 7188219 (2007-03-01), Jeddeloh
patent: 7206857 (2007-04-01), Mammen et al.
patent: 7251702 (2007-07-01), Lee et al.
patent: 7266083 (2007-09-01), Carnevale et al.
patent: 2001/0023469 (2001-09-01), Jeong et al.
patent: 2002/0146023 (2002-10-01), Myers
patent: 2006/0015672 (2006-01-01), Boily
patent: 2006/0143345 (2006-06-01), Fredriksson
patent: 2006/0235648 (2006-10-01), Zheltov et al.
patent: 2010/0138839 (2010-06-01), Bekooij et al.
patent: 63251854 (1988-10-01), None
patent: 2-010459 (1990-01-01), None
patent: 03008196 (1991-01-01), None
patent: 4-322353 (1992-11-01), None
patent: 5-094409 (1993-04-01), None
patent: 06131307 (1994-05-01), None
patent: 09-062579 (1997-03-01), None
patent: 10055337 (1998-02-01), None
patent: 2000201161 (2000-07-01), None
patent: 2005258576 (2005-09-01), None
Mukherjee et al., “A Comparative Study of Arbitration Algorithms for the Alpha 21364 Pipelined Router”, Oct. 2002, ACM Press, Proceedings of the 10th International Conference on Architectural Support for Programming Languages and Operating Systems, pp. 223-234.
Schultz et al., “Multicast Contention Resolution with Single-Cycle Windowing Using Content Addressable FIFO's”, Oct. 1996, IEEE Press, IEEE/ACM Transactions on Networking (TON), vol. 4, Issue 5, pp. 731-742.
SeungJin et al., “Reservation-based Weighted Round Robin for Differentiated Services in TDMA networks,” Jul. 9-13, 2006, IEEE, The Joint International Conference on Optical Internet and Next Generation Network, pp. 199-201.
Yun-Lung et al., “A High-Speed and Decentralized Arbiter Design for NoC,” May 10-13, 2009, IEEE, IEEE/ACS Internation Conference on Computer Systems and Applications, pp. 350-353.
Landsberg et al., “Generic Queue Scheduling: Concepts and VLSI,” Jun. 12-16, 1994, IEEE, 13thProceedings of IEEE Networking for Global Communications, vol. 3, pp. 1438-1445.
Kangas et al., “TDMA-Based Communication Scheduling in System-on-Chip Video Encoder,” 2002, IEEE, IEEE International Symposium on Circuits and Systems, vol. 1, pp. I-369-I-372.
Canon Kabushiki Kaisha
Zaman Faisal M
LandOfFree
Device for arbitrating bus accesses and method for... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Device for arbitrating bus accesses and method for..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Device for arbitrating bus accesses and method for... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-4310316