Electrical computers and digital data processing systems: input/ – Interrupt processing – Interrupt prioritizing
Reexamination Certificate
2001-05-02
2004-08-03
Dang, Khanh (Department: 2111)
Electrical computers and digital data processing systems: input/
Interrupt processing
Interrupt prioritizing
C710S265000, C710S269000
Reexamination Certificate
active
06772260
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates generally to a device and method for generating interrupt signals to be applied to a CPU and for requesting an interrupt process. This invention relates more specifically to such a device and method for outputting a number of interrupt signals based on a plurality of interrupt events.
2. Description of the Related Art
Many recent electronic apparatuses have an energy-saving low power consumption mode (referred to as a “low power mode” below) that reduces power consumption by, for example, lowering the display brightness when the keyboard is not operated for a specific period of time, and/or by stopping power supply to an I/O device when there is no I/O access for a specific period of time. It will be noted that “low power mode” as used herein means a mode in which only some functions of the apparatus are enabled while others are disabled, i.e., power supply to and operation of the major part of the apparatus is temporarily stopped.
Furthermore, this low power mode generally shifts control to the normal operating mode when, for example, the keyboard is operated or an I/O access request is received, and power supply to the entire apparatus is restored.
JP-A-8-249081 and JP-A-5-32018, for example, teach a method for putting a high power consumption CPU into a sleep mode as a means of effectively reducing energy consumption. It should be noted that, in general, a CPU sleep mode is a state in which the CPU operating clock is stopped and signals applied to only some of the terminals, such as interrupt ports, can be detected (the CPU itself is not able to run any operating processes). A sleep mode is a low power mode advanced to the state where the CPU clock is stopped.
The above-noted prior art documents describe state transitions between modes, such as between a normal operating mode and a sleep mode. They are not clear, however, about how to control plural overlapping interrupt events and handling subsequent interrupt events while an interrupt process triggered by an earlier interrupt event is being executed. In addition to steadily increasing functional complexity, recent electronic apparatuses must also be able to set and handle a large number of interrupt events to, for example, effect state changes between a normal operating mode and a low power mode and between various low power modes including a sleep mode. There are even applications in which dozens of interrupt events must be handled.
When there are plural and particularly when there are dozens of interrupt events, controlling which interrupts to pass to the CPU under what conditions is an important factor relating to apparatus performance, that is, efficiently and appropriately operating the apparatus. A 1:1 relationship between interrupt events and interrupt signals is often not possible because the CPU has only a limited number of interrupt ports.
Depending upon the operating conditions, it may also be desirable to change the priority with which interrupt signals generated in response to particular interrupt events are processed by the CPU. For example, more efficient processing could be achieved in some cases by assigning a high priority to interrupt events unique to the sleep mode when the sleep mode is entered. It may also be useful to dynamically set or change the priority of processing interrupt events according to changes in the operating environment, such as changing interrupt event priority or disabling some interrupt events in response to an error state.
Under what specific conditions an interrupt will be generated, and what priority will be assigned to the interrupt, will vary according to the error or other cause of the interrupt and the frequency of the interrupt. If a problem occurs in the power supply, for example, it is necessary to immediately issue a specific warning and to take other measures as necessary, such as turning off the power supply. On the other hand, removing the ink tank from an ink jet printer or opening the cover when the printer's CPU is in a sleep mode are events of low urgency. In cases such as these the sleep mode can be maintained until an operating command is asserted, and the normal operating mode can be resumed when an interrupt event of greater importance occurs. It is thus preferable to be able to flexibly change interrupt signal priority.
Furthermore, when one interrupt is being handled and another interrupt request (of the same priority) is applied to the same interrupt port used for the interrupt being currently handled, the latter interrupt request may be ignored and an essential interrupt process will not be executed.
It is also possible to change interrupt event priority according to the operating mode of the apparatus (whether the CPU of the apparatus is in the sleep mode or other operating mode, for example). To accomplish this, however, it must be possible to change the interrupt priority in the mode transition process changing the operating mode. What events (changes in condition) cause the CPU to resume the normal operating mode will differ according to the basic design concept of the apparatus and what types of functions are provided in the apparatus. A high degree of freedom is therefore desirable for setting interrupt conditions.
A first object of this invention is to provide a device and method for generating interrupt signals that allow to statically or dynamically set the priority of interrupt signals generated in response to various interrupt events.
A further object of this invention is to provide such device and method capable of generating a number of interrupt signals from a larger number of interrupt events.
A yet further object of this invention is to provide such device and method whereby an appropriate handling process can be run when an interrupt event occurs while a previous interrupt of the same priority is being handled.
SUMMARY OF THE INVENTION
Embodiments of the present invention can change the priority of interrupt signals generated in response to plural event detection signals that represent interrupt events, can generate from the plural event detection signals a smaller number of interrupt signals, and, when an event detection signal is received during the execution of a current interrupt process, can perform another interrupt process appropriate to the received event detection signal after the current interrupt process ends, and thus resolves the above-described problems of the prior art.
It should be noted that interrupt signal priority as used herein corresponds to the number of interrupt ports available on a CPU such that if a CPU has four interrupt ports, for example, a maximum of four priority levels can be assigned to interrupt signals. It is normally possible to assign a priority level to each interrupt port of a CPU relative to its other interrupt ports. Embodiments of the present invention can set or change the priority level of interrupt signals generated from plural event detection signals according to the priority of the respective interrupt events, and re-assign interrupt signals to interrupt ports in the order of changing priority. In other words, these embodiments set the priority of interrupt signals generated from plural event detection signals, and can change interrupt signal priority.
REFERENCES:
patent: 4972312 (1990-11-01), den Boef
patent: 5146595 (1992-09-01), Fujiyama et al.
patent: 5581668 (1996-12-01), Oida et al.
patent: 5708819 (1998-01-01), Dunnihoo
patent: 5892959 (1999-04-01), Fung
patent: 0 884 684 (1998-12-01), None
patent: 5-32018 (1993-02-01), None
patent: 08-249081 (1996-09-01), None
patent: WO 99/34298 (1999-07-01), None
Imai Satoru
Kawase Yuji
Dang Khanh
Rosalio Haro
Seiko Epson Corporation
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