Device for addressing of redundant elements of an integrated cir

Details Device for addressing of redundant elements of an integrated cir Device for addressing of redundant elements of an integrated cir

1990-01-17

1991-10-15

Popek, Joseph A.

Static information storage and retrieval

Read/write circuit

Bad bit

371 103, G11C 700

Patent

active

050580698

ABSTRACT:
A device for the addressing of redundant elements of an integrated circuit memory is disclosed. This memory comprises an array of row memory elements and column memory elements, respectively addressable by row addresses and column addresses, and at least one group of fuses to store the address of a faulty element of the memory. Each fuse is associated with a row/column address pair. Through the blowing of certain fuses in the group after testing of a memory element, the address either of a column element, if the faulty element is a column element, or of a row element, if the faulty element is a row element, is stored. Only the row addresses are enabled when the stored address is that of a row element, and only the column addresses are enabled when the stored address is that of a column element, in order to address either a row redundant element or a column redundant element.

REFERENCES:
patent: 4635190 (1987-01-01), Meyer et al.
Patent Abstracts of Japan, vol. 8, No. 151 (P-286) [1588], 13 Jul. 1984; & JP-A-59 48 898 (Hitachi Seisakusho K. K. 21-03-1984.
Processing of the IEEE, vol. 74, NO. 5, May 1986, pp. 684-698, IEEE, New York, U.S.; W. R. Moore: "A Review of Fault-Tolerant Techniques for the Enhancement of Integrated Circuit Yeild" *page 684, col. 2, Line 22-col. 2, line 16*.

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