Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2006-08-08
2006-08-08
Siek, Vuthe (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000, C716S030000, C716S030000
Reexamination Certificate
active
07089522
ABSTRACT:
A design, device, system and process for placing slots in active regions (e.g., metal areas). Embodiments of the present invention improve the planarization of metal areas (e.g., lines) and insulators by reducing depressions (e.g., dishing) in the metal areas by including symmetric or square slots inside selected wide metal lines, by adhering to a set of placement rules. Embodiments reduce dishing in copper dual damascene structures. Embodiments reduce data processing requirements for designing and arranging the layout of IC devices and the slots.
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Andrew B. Kahng et al., “Filling and Slotting: Analysis and Algorithms”, ISPD 98 Monterey CA USA, p. 95-102.
Chua Tat Wei
Tan Patrick
Tee Kheng Chok
Vigar David
Chartered Semiconductor Manufacturing Ltd.
Siek Vuthe
Stoffel William J.
To Tuyen
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