Device control register for a processor block

Details Device control register for a processor block Device control register for a processor block

2008-04-04

2010-06-15

Tan, Vibol (Department: 2819)

Electronic digital logic circuitry

Multifunctional or programmable

Array

C713S100000

Reexamination Certificate

active

07737725

ABSTRACT:
A device control register controller for a processor block Application Specific Integrated Circuit (“ASIC”) core is described. Device control register slave blocks are coupled to the device control register controller and have access to device registers for a plurality of interfaces of the processor block ASIC core. A master device interface is for coupling at least one slave device external to the processor block ASIC core to the device control register controller. A slave device interface is for coupling a master device external to the processor block ASIC core to the device control register controller.

REFERENCES:
patent: 6262596 (2001-07-01), Schultz et al.
patent: 7266680 (2007-09-01), Reinbold
patent: 7518396 (2009-04-01), Kondapalli et al.
U.S. Appl. No. 12/043,097, filed Mar. 5, 2008, Ansari, Ahmad R., et al., entitled “A Processor Block Asic Core for Embedding in an Integrated Circuit”, Xilinx, Inc. 2100 Logic Drive, San Jose, California 95124.
UG200 (v1.1), “Embedded Processor Block in Virtex-5 FPGAs”, Mar. 31, 2008, 323 pages, Xilinx, Inc. 2100 Logic Drive, San Jose, CA 95124.

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