Device and process involving pinhole undercut area

Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode

Reexamination Certificate

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C257S040000, C257S288000, C257S621000, C257SE51006

Reexamination Certificate

active

07821068

ABSTRACT:
An electronic device fabrication method including: (a) providing a dielectric region and a lower electrically conductive region, wherein the dielectric region includes a plurality of pinholes each with an entry and an exit; and (b) depositing an etchant for the lower electrically conductive region into the pinholes that undercuts the pinholes to create for a number of the pinholes an overhanging surface of the dielectric region around the exit facing an undercut area of the lower electrically conductive region wider than the exit.

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patent: 6765279 (2004-07-01), Leedy
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patent: 7709302 (2010-05-01), Nakajima
patent: 2002/0011627 (2002-01-01), Takemura et al.
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patent: 2006/0138427 (2006-06-01), Yamazaki et al.
patent: 2007/0063180 (2007-03-01), Asano et al.
patent: 2007/0128758 (2007-06-01), Tanaka et al.
patent: 2007/0247064 (2007-10-01), Hosokawa
patent: 2010/0006826 (2010-01-01), Dimmler

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