Electrical computers and digital processing systems: memory – Storage accessing and control – Control technique
Reexamination Certificate
2000-01-21
2002-12-10
Yoo, Do Hyun (Department: 2187)
Electrical computers and digital processing systems: memory
Storage accessing and control
Control technique
C711S152000, C711S103000, C714S718000, C714S738000, C365S201000
Reexamination Certificate
active
06493808
ABSTRACT:
FIELD OF THE INVENTION
The invention relates to a device for testing a reprogrammable non-volatile memory having dedicated areas which can be protected in reading, writing and/or erasing. It also relates to the process used in said device for testing the integrality of the memory before it is made available to the user for the application for which it is intended.
The invention has applications in all fields using a reprogrammable non-volatile memory system, whose accesses are regulated. It can in particular be used in contactless identification systems such as identification labels for tracking objects or for remote ticketing.
PRIOR ART
Reprogrammable non-volatile memory systems having dedicated areas protectable in reading, writing and/or erasing comprise means for controlling access rights to said areas. These means consist of a control logic integrating hardware or software fuses authorizing or not authorizing reading, writing and/or erasing or clearing of all or part of the content of said areas.
Hardware fuses which are very reliable with respect to fraud suffer from the disadvantage of requiring a breakdown overvoltage which, in certain applications, is not available. This is particularly the case in most contactless identification systems.
So-called software fuses consist of one or more reprogrammable non-volatile memory bits, known as latch bits. In the case of a memory having e.g. several dedicated areas protected in writing and erasing, the latch bit of each area authorizes or does not authorize access of said area in writing and erasing. For example, if the bit is at “0”, the memory area dependent on said latch bit is accessible in writing and erasing and if it is at “1” said memory area is neither accessible in writing nor in erasing. However, no matter what the value of the latch bit, the memory area in question is accessible in reading, because reading does not form the object of any protection.
However, this type of protection causes a problem during the initialization of the memory prior to its use for the target application to which it is intended, i.e. before being made available to the user. Thus, at the end of manufacture, the memory has a random configuration, i.e. the bits can be either at “0” or “1”. It is therefore necessary to initialize the memory, which requires accessing all the areas of the memory, no matter what the value of the latch bits.
Two methods are generally used for solving the memory initialization problem.
The first method consists of adding to the memory test pads making it possible to directly access the memory by presetting certain states in the control logic, i.e. certain latch bits.
However, in the case of integrated circuits, the introduction of these specific test bits increases the size of the circuits and requires a supplementary test stage at the end of the production line, which increases the circuit manufacturing costs.
The second method described in U.S. Pat. No. 5,394,367 consists of using a configuration word. This configuration word is a set of saved bits in a configuration area of the memory. It protects the access to the latch bits in the following way. When the configuration word differs from a blocking value defined by the user, all the protected areas are accessible in reading, writing and erasing. When the configuration word is identical to the blocking value, the access rights to the protected areas are regulated by the latch bits. The probability that the blocking value is that of the configuration word at the end of manufacture becomes smaller as the number of bits becomes larger and the blocking value is well chosen. This method does not require the introduction of any supplementary element and makes it possible to minimize the surface area of the integrated circuits and simplify the implementation of the initialization phase.
However, apart from the initialization of the memory, prior to the use of the memory in its target application, it is also necessary to check the satisfactory operation of all the elements of the memory and also the control logic controlling accesses to the memory. This check must be carried out, preferably in an exhaustive manner. For this purpose, it is necessary to be able to modify at random the entire memory (including the configuration area) and test all the states of the control logic and in particular those imposed by the particular values of the configuration area. However, the method described in U.S. Pat. No. 5,394,467 does not permit such a verification (or memory testing). It only permits an operation in the so-called “normal” checking mode of the memory access rights.
DESCRIPTION OF THE INVENTION
The object of the invention is to solve the problems of the procedures described hereinbefore. To this end, it proposes a process and a device permitting an operation in two modes, namely a “test” mode, in which all the memory areas are accessible no matter what the protection of said areas, which makes it possible to perform an exhaustive test on the memory and control logic and a “normal” mode in which access protections are irreversible, the configuration area then only being modifiable in the case where the access restrictions to the areas are increased.
More specifically, the invention relates to a device for testing a reprogrammable non-volatile memory having dedicated areas protectable in reading and/or writing and/or erasing and whose access rights consist of configuration words saved in a configuration area of the memory, said device comprising message transition/reception means and a received message logic control unit and memory access controls, characterized in that it comprises at least one temporary register ensuring an emulation of these access rights so as to make the access protections reversible when the memory is in a “test” mode and irreversible in other cases.
Advantageously, the temporary register comprises:
a configuration register having an identical size and structure to the configuration area of the memory and
a test indication register.
The invention also relates to a process for testing a reprogrammable non-volatile memory using the above device. This process is characterized in that it comprises:
a) reading the content of the memory configuration area, transferring the said content into the temporary register and initializing the test indication register,
b) effecting at least one modification control of the configuration register of the temporary register whilst checking the access rights contained in the temporary register,
c) testing the modification of the configuration register by reading and/or writing and/or erasing controls on the memory areas in question.
Between stages a and b, the process according to the invention consists of comparing the value of the temporary register with one or more previously defined blocking values written into the control logic (
11
) and, when said two values are equal, making modifications to the configuration area irreversible and when they are different, authorizing reversible modifications of the configuration area. In other words, only the value of the memory configuration word (MCM) controls the latching or non-latching of the access rights.
According to an embodiment of the invention are immediately taken into account, the new content of the configuration area being immediately transferred into the temporary register.
According to another embodiment, the configuration area modification controls are taken into account in deferred manner by the temporary register, i.e. when the “correct supply” signal is again activated.
REFERENCES:
patent: 4975870 (1990-12-01), Knicely et al.
patent: 5175840 (1992-12-01), Sawase et al.
patent: 5264742 (1993-11-01), Sourgen
patent: 5345413 (1994-09-01), Fisher et al.
patent: 5394467 (1995-02-01), Kepley, III et al.
patent: 5826007 (1998-10-01), Sakaki et al.
patent: 5890191 (1999-03-01), Espinor et al.
Billiot Gérard
Crochon Elisabeth
Commissariat a l'Energie Atomique
Moazzami Nasser
Pearne & Gordon LLP
Yoo Do Hyun
LandOfFree
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