Device and process for detecting errors in an integrated...

Error detection/correction and fault detection/recovery – Pulse or data error handling – Testing of error-check system

Reexamination Certificate

Rate now

  [ 0.00 ] – not rated yet Voters 0   Comments 0

Details

C714S041000

Reexamination Certificate

active

06173423

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a device and a process for detecting errors in an integrated circuit comprising a parallel-serial and serial-parallel port.
2. Description of Related Art
Integrated circuits are known which comprise interfaces between a parallel bus and a serial bus, but in general these do not include a device and process for detecting and recovering from errors, since they are based on the assumption that the communication does not comprise any errors involving the serial link, or if it does comprise any, the detections of errors and recoveries from errors are handled in a higher layer (synchronization loss) at the software level.
SUMMARY OF THE INVENTION
In the invention, the serial link is a 1-gigabaud serial link, and it is assumed that two ports of the same type are communicating with one another through the serial link. It is further assumed that machines whose error rate in terms of message corruption and calibration loss and/or protocol inconsistency is on the order of 10
−17
communicate with one over the link. It is noted, taking into account the speed of the serial link and the error rate of the machine, that this seemingly low error rate can result in a substantial error and an abnormal operation of the machine every two days.
Therefore, a first object of the invention is to provide a serial-parallel link interface in both directions for an integrated circuit, thus allowing the detection of errors and the verification of the proper operation of the communication over the serial-parallel link.
This object is achieved due to the fact that the error detecting device is in an integrated circuit comprising a serial link control function constituting an input-output port between a parallel bus and a serial link. The integrated circuit comprises a serializer circuit on output and a deserializer circuit on input and includes an insertion buffer has each of its outputs connected to an exclusive OR operation with two inputs, each second input of which receives a piece of information to be transmitted in order to constitute, with the insertion information issuing from the insertion buffer, a piece of substitute information, and an additional buffer that makes it possible to compare the sequence supplied as output from the exclusive OR with a sequence stored in the additional buffer, in order to validate the transmission of the substitute sequence.
According to another characteristic, the additional buffer includes a validity bit and the sequence to be compared.
According to another characteristic, the sequence to be compared can be a token, a CRC, data, ends of frame, an idle message or idle character.
According to another characteristic, the port comprises a serial link that loops the output of the serializer back to the input of the deserializer, which serial link is validated by a loop command entry supplied by a control register.
According to another characteristic, the port comprises on output from the deserializer a history buffer that stores either the last 16 control characters coming from the serial link through a decoder, or the last 16 control characters except for the idle characters.
According to another characteristic, the characters stored in the history buffer are used by the integrated circuit to determine the cause of a detected error.
According to another characteristic, the port comprises at least one incoming buffer (TDBUT) for data to be transmitted from the parallel bus and at least one outgoing buffer (RDBUF) for data to be received, and comprises, between the at least one incoming buffer (TDBUF) and the outgoing serializer circuit, and between the at least one outgoing buffer (RDBUF) and the incoming deserializer, respectively, a CRC code generating circuit for each respective transmitting part and a CRC code checking circuit for each respective receiving part.
According to another characteristic, the serializer and deserializer circuits run at 1 gigabaud, the speed of the serial link.
According to another characteristic, the CRC generating circuit delivers a 16-bit word by using a cyclic permutation algorithm to calculate the CRC after the shift corresponding to the control of a nine-bit byte.
According to another characteristic, the data transmitting or receiving buffers (TDBUF, RDBUF) run on the system clock having a frequency that corresponds to the frequency of the internal bus of the integrated circuit.
According to another characteristic, a serially transmitting 9/12 encoder circuit is coupled with the serializer, and a receiving 9/12 decoder circuit is coupled with the deserializer in order to transform a normal 9-bit character and a control character into 12-bit code which, on reception, allows the extraction of the clock signal and an idle DC component from the transmission.
Another object of the invention is to provide a process for detecting errors.
This object is achieved due to the fact that the process for detecting errors in a high-speed serial-parallel communication port and a CRC circuit comprising an error injecting mechanism is characterized in that it comprises:
a step for sending to the port a piece of information to be transmitted;
a step for calculating the CRC from the information to be transmitted and for storing the CRC corresponding to the information to be transmitted;
a step for generating a piece of erroneous information by validating the error injecting mechanism, and a step for transmitting the erroneous information to an integrated circuit equipped with the same type of port;
a step for detecting data errors by means of the CRC checking circuit of the receiving port;
a step for sending an interrupt message to the integrated circuit of the transmitting port;
a step for reading, by means of a microprocessor connected to the parallel bus of the transmitting port, the value calculated by the CRC circuit of the receiving port;
a step for comparing the stored value to the read value.
According to another characteristic, the process includes a step for looping the transmitting serializer circuit back to the receiving deserializer circuit of the same port of the integrated circuit.
According to another characteristic, the error injecting mechanism comprises:
a step for storing, in an injection buffer, injection information to be combined with the transmitted information so as to generate the error;
a step for loading an activation buffer of the injecting mechanism comprising a sequence of one or two characters;
a step for substituting the substitute information resulting from the combination of the transmitted information with the injection information as soon as the transmitted information corresponds to the information from the activation buffer.
According to another characteristic, the length of the substitute sequence is limited to 8 characters.


REFERENCES:
patent: 4712215 (1987-12-01), Joshi et al.
patent: 4827477 (1989-05-01), Avaneas
patent: 4907225 (1990-03-01), Gulick et al.
patent: 4935925 (1990-06-01), Williams et al.
patent: 5394390 (1995-02-01), Stauffer et al.
patent: 5581559 (1996-12-01), Crayford et al.
patent: 5754525 (1998-05-01), Lo et al.
patent: 5907566 (1999-05-01), Benson et al.
patent: 2097653 (1982-03-01), None
Patent Abstracts of Japan vol. 010, No. 223 (P-483), Aug. 5, 1986 & JP 61 059547 A (Yokogawa Hokushin Electric Corp), Mar. 27, 1986, Abstract.
Patent Abstracts of Japan vol. 008, No. 269 (P-319), Dec. 8, 1984 & JP 59 136843 A (Yokogawa Hokushin Denki KK), Aug. 6, 1984, Abstract.
C.J. Georgiou et al.: “Scalable Protocol Engine For High Bandwidth Communications”, 1997 IEEE Int. Conf. On Communications, vol. 2, Jun. 8, 1997, Montreal, Quebec, Canada pp. 1121-1126, XPOO2060851.
Richard Nass: “Fibre Channel Transceiver UPS Bandwidth, Maintains Design Ease.” Electronic Design, vol. 45, No. 10, May 12, 1997, USA, pp. 69-72, XP000698867.
G.R. Stephens et al.: Fibre Channel The Basics 1995, Ancot Corp., Menlo Park, CA., USA XP002060314, pp 1-0—1-14 6-0—8-17.
C.J. Hossack et al.: “Fully Interconnected Fault-Tolerant Networks

LandOfFree

Say what you really think

Search LandOfFree.com for the USA inventors and patents. Rate them and share your experience with other people.

Rating

Device and process for detecting errors in an integrated... does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Device and process for detecting errors in an integrated..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Device and process for detecting errors in an integrated... will most certainly appreciate the feedback.

Rate now

     

Profile ID: LFUS-PAI-O-2479373

  Search
All data on this website is collected from public sources. Our data reflects the most accurate information available at the time of publication.