Device and method of reducing word line resistance of a semicond

Details Device and method of reducing word line resistance of a semicond Device and method of reducing word line resistance of a semicond

1992-12-03

1995-11-14

Nelms, David C.

Static information storage and retrieval

Addressing

Particular decoder or driver circuit

365 63, 365104, G11C 800, G11C 700

Patent

active

054673160

ABSTRACT:
A semiconductor memory device with a memory array of cells formed as a matrix has bit lines, and word lines driven by word line drivers, where each of the word line drivers simultaneously selects and drives at least two word lines in order to minimize line resistances of the word lines, thereby minimizing a delay time and improving a speed of sensing a cell data. Accordingly a number of the word line drivers is at least one-half a number of the word lines.

REFERENCES:
patent: 4883980 (1989-11-01), Morimoto et al.
patent: 4906872 (1990-03-01), Tanaka
patent: 4926378 (1990-05-01), Uchida et al.
patent: 4958092 (1990-09-01), Tanaka
patent: 5053993 (1991-10-01), Miura
patent: 5075890 (1991-12-01), Itoh et al.
patent: 5097440 (1992-03-01), Konishi et al.
patent: 5097441 (1992-03-01), Cho et al.
patent: 5148401 (1992-09-01), Sekino et al.
patent: 5172335 (1992-12-01), Sasaki et al.

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