Device and method of manufacture for an integrated circuit havin

Active solid-state devices (e.g. – transistors – solid-state diode – Test or calibration structure

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257758, 257773, 257786, H01L 2348

Patent

active

059659033

ABSTRACT:
The present invention provides, in one embodiment, an integrated circuit having a substrate and active devices formed on the surface of the substrate. Other embodiments of the integrated circuit provide for having at least either three or four metal layers. In a particular embodiment of the present invention, the integrated circuit comprises a bond pad formed over a portion of the active devices. The bond pad has a footprint. As used therein the word footprint means the area covered by the device to which the word refers. The integrated circuit further incudes a patterned metal layer having a metal layer footprint that is located between the bond pad and the substrate and a built-in self-test (BIST) circuit that has a BIST footprint, which is located between the substrate and the bond pad. In this particular embodiment, the bond pad footprint overlays at least a portion of the metal layer footprint and the BIST footprint. However, in a more advantageous embodiment, the bond pad footprint overlays a substantial portion of the metal layer footprint and the BIST footprint.

REFERENCES:
patent: 4636832 (1987-01-01), Abe et al.
patent: 4984061 (1991-01-01), Matsumoto
patent: 5502337 (1996-03-01), Nozaki
K. Mukai, A. Hiraiwa, S. Muramatsu, I. Yoshida and S. Harada; "A New Integration Technology That Enables Forming Bonding Pads on Active Areas"; IEDM 1981; pp. 62-65.

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