Device and method of managing asynchronous events in a finite st

Details Device and method of managing asynchronous events in a finite st Device and method of managing asynchronous events in a finite st

1993-09-21

1995-02-14

Westin, Edward P.

Electronic digital logic circuitry

Clocking or synchronizing of logic stages or gates

326 46, 327141, H03K 1900, H03K 19173

Patent

active

053898389

ABSTRACT:
A finite state machine connected to a plurality of units which enables to manage the execution of M asynchronous signals to select one of these M asynchronous signals which may become a user clock at a moment which is independent from the pulse of the state machine clock within a minimum of time. The state machine comprises a combinational logic circuit (1) receiving a set of primary input signals (3) which contains N asynchronous input signals and outputting state variable output signals (6) to a state variable register (2). The register (2) is driven by a clock signal (7) which is the clock signal of the state machine and provides M state variable register output signals (51, 52) to M additional latches (10, 20) which delay the signal until they receive a timing pulse (71 or 72) from the combinational circuit. The moment when a pulse is generated is defined by one of the M equations determined by a particular need whose requirements are inputted among the set of primary input signals (3) in the combinational circuit, the equation may also depend on the variable which indicates the signal selected by means of line (50) looping back to combinational logic circuit so that said state machine may be used as a clock select selecting one of the clock input signal to become a user clock; and each time an equation is satisfied, the combinational circuit generates a timing pulse to the corresponding latch which generates then an output signal (53 or 54) to the different units and also to the combinational circuit to indicate the present state of the state machine. Those output signals (53, 54) may be used in connection with a selection means (110) to select which clock input signal is to become a user clock.

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patent: 5155380 (1992-10-01), Hwang et al.
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patent: 5204555 (1993-04-01), Graham et al.
patent: 5274281 (1993-12-01), Hay
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