Static information storage and retrieval – Read/write circuit – For complementary information
Reexamination Certificate
2002-10-24
2003-11-25
Le, Thong (Department: 2818)
Static information storage and retrieval
Read/write circuit
For complementary information
C365S189011
Reexamination Certificate
active
06654297
ABSTRACT:
TECHNICAL FIELD OF THE INVENTION
The present invention relates in general to memory arrays and in particular to storing two bits for each data bit in a memory array.
BACKGROUND OF THE INVENTION
Memory devices are typically provided as internal storage areas in the computer. There are several different types of memory. One type of memory is random access memory (RAM) that is typically used as main memory in a computer environment. Most RAM is volatile, which means that it requires a steady flow of electricity to maintain its contents.
A dynamic random access memory (DRAM) is a type of RAM. A DRAM memory is made up of memory cells. Each cell or bit includes a transistor and a capacitor. A cell is capable of storing information in the form of a “1” or “0” bit as an electrical charge on the capacitor. Since a capacitor will lose its charge over time, a memory device incorporating a DRAM memory must include logic to refresh (recharge) the capacitors of the cells periodically or the information will be lost. Reading the stored data in a cell and then writing the data back into the cell at a predefined voltage level refreshes a cell. The required refreshing operation is what makes DRAM memory dynamic rather than static.
While a cell is being refreshed it cannot be read by a processor. This causes systems incorporating DRAMS to be slower than systems incorporating RAMS. However, DRAMS are more commonly used than RAMS because their circuitry is simpler and because they can hold up to four times as much data. Another disadvantage in using a typical DRAM is the amount of power needed to constantly refresh the cells. This disadvantage becomes more crucial as apparatuses incorporating memory devices are designed to use less and less power.
For the reasons stated above, and for other reasons stated below which will become apparent to those skilled in the art upon reading and understanding the present specification, there is a need in the art for a DRAM memory device whose cells can go for an extended period of time without having to be refreshed
SUMMARY OF THE INVENTION
The above-mentioned problems with non-volatile memory devices and other problems are addressed by the present invention and will be understood by reading and studying the following specification.
In one embodiment, a method of operating a DRAM memory array having a plurality of memory cells wherein, in a plan view, each memory cell has an area of less than 8F
2
comprises storing a first bit in a first memory cell, and storing a second bit that is complementary to the first bit in a second memory cell. The method includes pre-charging and equilibrating first and second digit lines to an intermediate voltage level, sharing a charge on a capacitor of the first memory cell with the first digit line, and sharing a charge on a capacitor of the second memory cell with the second digit line. A voltage difference between the first digit line and the second digit line is compared with a sense amplifier.
REFERENCES:
patent: 4112512 (1978-09-01), Arzubi et al.
patent: 4459685 (1984-07-01), Sud et al.
patent: 4601019 (1986-07-01), Shah et al.
patent: 5144584 (1992-09-01), Hoshino
patent: 5291443 (1994-03-01), Lim
patent: 5339273 (1994-08-01), Taguchi
patent: 5373475 (1994-12-01), Nagase
patent: 5381368 (1995-01-01), Morgan et al.
patent: 5422850 (1995-06-01), Sukegawa et al.
patent: 5440517 (1995-08-01), Morgan et al.
patent: 5461587 (1995-10-01), Oh
patent: 5469393 (1995-11-01), Thomann
patent: 5471430 (1995-11-01), Sawada et al.
patent: 5502675 (1996-03-01), Kohno et al.
patent: 5528539 (1996-06-01), Ong et al.
patent: 5555212 (1996-09-01), Toshiaki et al.
patent: 5592428 (1997-01-01), Harrand et al.
patent: 4601019 (1997-09-01), Shah et al.
patent: 5689465 (1997-11-01), Sukegawa et al.
patent: 5689467 (1997-11-01), Hashimoto
patent: 5724286 (1998-03-01), Gillingham
patent: 5754486 (1998-05-01), Nevill et al.
patent: 5781483 (1998-07-01), Shore
patent: 5936874 (1999-08-01), Clampitt et al.
patent: 6005816 (1999-12-01), Manning et al.
patent: 6044029 (2000-03-01), Shore
patent: 6075737 (2000-06-01), Mullarkey et al.
patent: 6075743 (2000-06-01), Barth et al.
patent: 6122213 (2000-09-01), Shore
patent: 6243311 (2001-06-01), Keeth
patent: 6285618 (2001-09-01), Shore
patent: WO 97/28532 (1997-08-01), None
Keeth et al., “DRAM Circuit Design,” IEEE Press, 2001, pp. 35-43.
Le Thong
Leffert Jay & Polglaze P.A.
Micro)n Technology, Inc.
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