Electrical computers and digital processing systems: memory – Storage accessing and control – Specific memory composition
Reexamination Certificate
2002-01-29
2003-12-16
Peikari, B. James (Department: 2186)
Electrical computers and digital processing systems: memory
Storage accessing and control
Specific memory composition
C711S150000, C711S220000, C370S360000, C370S363000, C710S031000
Reexamination Certificate
active
06665770
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention generally relates to a pointer register device for retaining a pointer value (i.e., an address for accessing a memory), updating the pointer value by arithmetic operation, and the like in, e.g., a processor included in a computer. More particularly, the present invention relates to a pointer register device including a register called a shadow register (back register) and a method for updating a pointer value.
2. Description of the Related Art
For example, a processor included in a computer includes registers for retaining a pointer value (i.e., an address for accessing a memory). The registers can be accessed more rapidly than the memories. Therefore, the registers are used to store a pointer value that is frequently or continuously referred to. As the processing of the processor is complicated, the number of pointer values to be stored in the registers is also increased. If the number of pointer values to be stored in the registers exceeds the number of registers that are actually included in the processor, data transfer must be frequently conducted between the registers and the memory, degrading the processing efficiency. If the number of registers is increased, the number of instructions and the instruction length are also increased. In other words, the number of instructions must be increased according to the increase in the number of registers, and the instruction length must be increased in order to specify the register in each instruction. This complicates the hardware and the circuit scale.
A known method to increase the substantial number of registers without increasing the apparent number of registers (i.e., the number of registers when viewed from the software) is to provide registers called shadow registers or back registers. In this method, the processor includes a register set (including two registers) capable of being accessed in an alternative manner, instead of a commonly used independent register. In this case, the same instruction set is used as that in the case where there is only a selected register, except that it includes an instruction to select one of the registers. The resultant processing capability is approximately the same as that obtained when the number of registers is increased. Moreover, this processing capability can be obtained without causing disadvantages like a complicated instruction set. Note that the term “register set” herein refers to a set of registers that are used in an alternative manner. Therefore, the “register set” is different from a “register pair”, i.e., a pair of registers that are used together as a single register having a double bit length.
In a known configuration using such a register set, a base value is retained in the non-selected register and the base value plus or minus a prescribed offset value is stored in the selected register for later reference. This configuration makes good use of the two registers and enables efficient operation of the offset. Moreover, since it is only the selected register that can be directly accessed by an instruction, this configuration can be implemented without complicating the instruction set.
Hereinafter, the specific structure of a conventional pointer register device including such a register set will be described.
FIG. 6
is a circuit diagram of the structure of a conventional pointer register device.
In
FIG. 6
, a front/back register set
201
includes a first register
201
a
and a second register
201
b
for retaining a pointer value. The front/back register set
201
is basically recognized as a single register when viewed from the outside of the pointer register device (i.e., from a program instruction). Either the register
201
a
or
201
b
selected according to the program instruction is accessed. In other words, in reading and writing a pointer value, the registers
201
a
,
201
b
need not be distinguished from the outside. (Note that the terms “front” and “back” are merely used to distinguish the selected register from the non-selected one, and are not used to fixedly distinguish between the first and second registers
201
a
,
201
b
.)
A transfer switch set
202
includes switches
202
a
,
202
b
respectively corresponding to the registers
201
a
,
201
b
. The transfer switch set
202
selects either writing the addition result of an adder
205
or a pointer value applied from the outside of the pointer register device, or transferring a pointer value between the registers
201
a
,
201
b
(i.e., writing a pointer value retained in one register to the other).
A transfer path
203
is a signal path for transferring a pointer value between the registers
201
a
,
201
b.
A register select switch set
204
includes a read select switch
204
a
and a write select switch
204
b
. The register select switch set
204
selects either the register
201
a
or
201
b
in order to read or write a pointer value.
The adder
205
adds a pointer value retained in the register
201
a
,
201
b
and an additional value applied from the outside of the pointer register device.
An adder select switch
206
selects either the addition result of the adder
205
or a write pointer value applied from the outside of the pointer register device for input to the front/back register set
201
.
A switch control section
207
controls the respective switching states of the transfer switch set
202
, the register select switch set
204
and the adder select switch
206
. For example, the switch control section
207
retains information designating the register (
201
a
or
201
b
) from or to which a pointer value is to be read or written, and outputs a switch signal S based on that information to switch the register selector switch set
204
.
A program-instruction execution control section
208
controls operation of each part based on a program instruction. When executing a program instruction to switch to the register
201
a
,
201
b
, the program-instruction execution control section
208
instructs the switch control section
207
to switch the register select switch set
204
accordingly. Basically, when executing other program instructions including an instruction to write or read a pointer value, the program-instruction execution control section
208
will not instruct the switch control section
207
to switch the register select switch set
204
. As described above, the pointer value is thus written to or read from either the register
201
a
or
201
b
that has already been selected. However, during the operations of updating a pointer value described below, the program-instruction execution control section
208
controls switching of the register select switch set
204
or the like as necessary.
Typical operations in the above pointer register device include: (A) “relative-pointer updating operation”; (B) “base-pointer updating operation”; and (C) “initial-pointer updating operation”. Hereinafter, these operations will be described specifically.
(A) Relative-Pointer Updating Operation
The relative-pointer updating operation (hereinafter, operation (A)) is the operation of replacing an original pointer value retained in the front/back register set
201
with a pointer value for actual access to a memory (i.e., an effective address). More specifically, the original pointer value retained in one register of the front/back register set
201
and a relative pointer value designated by a program instruction or the like are added, and the sum is written to that register.
Operation (A) will now be described specifically with reference to FIG.
7
. It is herein assumed that an original pointer value A retained in the first register
201
a
is to be replaced with the sum of the original pointer value A and an additional value C, i.e., (A+C).
(0) The respective switching states of the register select switch set
204
and the transfer switch set
202
are as shown in
FIG. 7
before operation (A). More specifically, the switches
204
a
,
204
b
select the first register
201
a
, and the switch
202
a
allows the su
Matsushita Electric - Industrial Co., Ltd.
McDermott & Will & Emery
Peikari B. James
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