Data processing: measuring – calibrating – or testing – Testing system – Signal generation or waveform shaping
Reexamination Certificate
2007-12-25
2007-12-25
Tsai, Carol S. W. (Department: 2857)
Data processing: measuring, calibrating, or testing
Testing system
Signal generation or waveform shaping
C702S057000, C702S183000
Reexamination Certificate
active
11372470
ABSTRACT:
A method and device for testing an electrical circuit, which do not require a thorough electrical circuit simulation but reliably identifying circuit faults. Preferred embodiments generate a fault signal that indicates that a given state of the circuit, which is defined by an electrical state variable, could occur in an electrical circuit. Generally, electrical components are individually treated as short-circuited or non-conducting regarding each pair of connections of the components. An electrical state variable is permanently allocated to at least one network node or a connecting pin of the electrical circuit. Electrical state variables of the network nodes and connecting pins of the components that are to be treated as short-circuited are allocated to each network node and each connecting pin. An assessment is made at least based on the allocated state variables as to whether the given circuit state can occur.
REFERENCES:
patent: 3851161 (1974-11-01), Sloop
patent: 4590472 (1986-05-01), Benson et al.
patent: 4837502 (1989-06-01), Ugenti
patent: 5488323 (1996-01-01), Beacham et al.
patent: 5588142 (1996-12-01), Sharrit
patent: 5831437 (1998-11-01), Ramadoss et al.
patent: 6570400 (2003-05-01), Habersetzer et al.
patent: 7073111 (2006-07-01), Whetsel
patent: 2003/0093504 (2003-05-01), Neunhoeffer et al.
patent: 2003/0120981 (2003-06-01), Neunhoeffer et al.
patent: 41 42 393 (1992-07-01), None
patent: 696 16 416 (1996-11-01), None
Delgado-Frias et al., ‘A Programmable Dynamic Interconnection Network Router with Hidden Refresh’, Nov. 1998, IEEE Publication, vol. 45, No. 11, pp. 1182-1190.
Lynch, ‘Measurement of Equivalent Electrical Circuit of a Piezoelectric Crystal’, Nov. 1949, POERS, pp. 323-331.
Bolsens, I., et al., “Electrical debugging of synchronous MOS VLSI circuits exploting analysis of the intended logic behaviour,” 26thACM/IEEE Design Automation Conference, Jun. 25-29, 1989, Paper 32.3, pp. 513-518.
Dagenais, M.R., et al., “Transistor-Level Estimation of Worst-Case Delays in MOS VLSI Circuits,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 11, No. 3, Mar. 1992, New York, US, pp. 384-395.
Hübner, U., et al., “Partitioning and Analysis of Static Digital CMOS Circuits,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 16, No. 11, Nov. 1997, pp. 1292-1310.
Auvergne, D., et al., “Formal Sizing Rules of CMOS Circuits,” IEEE 1991, pp. 96-100.
Usami, K., et al., “Clustered Voltage Scaling Technique for Low-Power Design,” Proceedings of the ACM International Symposium on Low Power Electronics and Design, 1995, pp. 3-8.
Baader Peter
Neunhoeffer Tilman
Desta Elias
Infineon - Technologies AG
Slater & Matsil L.L.P.
Tsai Carol S. W.
LandOfFree
Device and method for testing an electrical circuit does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Device and method for testing an electrical circuit, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Device and method for testing an electrical circuit will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3852110