Electrical computers and digital processing systems: memory – Storage accessing and control – Memory configuring
Reexamination Certificate
2001-02-15
2004-05-18
Kim, Matthew M. (Department: 2186)
Electrical computers and digital processing systems: memory
Storage accessing and control
Memory configuring
C714S037000, C714S045000
Reexamination Certificate
active
06738885
ABSTRACT:
TECHNICAL FIELD OF THE INVENTION
The present invention relates in general to processor debugging and analysis techniques and more particularly to a device and method for storing information in memory.
BACKGROUND OF THE INVENTION
In determining the cause of an error or failure during instruction execution by a processor, it is desirable to capture the state of the processor around the time the failure occurred. Conventional techniques for fault analysis include capturing information when triggered by the failure. However, this technique does not provide any information prior to the failure which is usually more helpful in analyzing the failure than the post failure data. Other techniques cannot effectively capture failure data when more than one failure occurs. Further, an out of order sequencing implementation may destroy the natural address order for captured information. This makes it difficult to recover the information pertaining to a failure. Therefore, it is desirable to have a technique that handles multiple failure occurrences while implementing an out of order sequence in memory.
SUMMARY OF THE INVENTION
From the foregoing, it may be appreciated by those skilled in the art that a need has arisen for a technique to capture information surrounding a triggering event. In accordance with the present invention, a device and method for storing information in a memory are provided that substantially eliminate or greatly reduce disadvantages and problems associated with conventional analysis techniques.
According to an embodiment of the present invention, there is provided a method for storing data in a memory that includes partitioning a memory space into a plurality of memory blocks. Received information is stored in a first set of the plurality of memory blocks. In response to a first triggering event, storing of received information in the first set of the plurality of memory blocks is halted. Received information is then stored in a second set of the plurality of memory blocks in response to the first triggering event. In this manner, information associated with a triggering event can be captured just prior to and just subsequent to the triggering event in order to analyze the cause and determine a solution for the triggering event.
The present invention provides various technical advantages over conventional analysis data gathering operations. For example, one technical advantage is to effectively capture prior and subsequent information associated with a triggering event. Another technical advantage is to effectively utilize and manipulate a limited memory space in capturing selected information. Yet another technical advantage is to be able to capture information in the presence of multiple triggering events. Still another technical advantage is to guarantee storage blocks for recording data prior to and subsequent to last triggering event in response to the occurrence of an unknown number of triggering events. Other technical advantages may be readily apparent to those skilled in the art from the following figures, description, and claims.
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Peltier Steven T.
Yeager Kenneth C.
Zhang David X.
Baker & Botts L.L.P.
Choi Woo H.
Kim Matthew M.
Silicon Graphics Inc.
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