Static information storage and retrieval – Addressing – Sync/clocking
Reexamination Certificate
2002-10-28
2003-11-18
Le, Thong (Department: 2818)
Static information storage and retrieval
Addressing
Sync/clocking
C365S194000, C365S226000
Reexamination Certificate
active
06650594
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Technical Field
The present invention relates to a device and method for controlling a semiconductor memory device and more particularly, to a circuit or memory device having a circuit for controlling a memory and controlling operations of the memory in selectable power down exit modes.
2. Discussion of Related Art
As operating speed and capacity of semiconductor memory devices continually increase, it is advantageous to incorporate memory control circuits such as a clock synchronization unit within the memory device. The clock synchronization unit is used for generating an internal clock signal in synchronization with an external clock signal such as a system clock. The internal clock is used to synchronously drive memory devices such as SDRAMs and DDR-SDRAMS. The clock synchronization unit can be a phase-locked loop (PLL), delay-locked loop (DLL), or duty-cycle correction circuit.
A PLL circuit typically includes a phase detector, a charge pump, a loop filter, and a voltage controlled oscillator (hereinafter referred to as “VCO”). By comparing phases of an external clock signal and an internal clock signal (i.e., an output of the VCO), the phase detector generates an up or down signal based on differences between the phases thereof, and transfers the up or down signal to the loop filter. The charge pump generates a constant output voltage according to the up or down signal, and transfers the constant output voltage to the loop filter. The loop filter filters the output voltage of the charge pump to eliminate a high frequency element, and outputs a control voltage for controlling the VCO. The VCO inputs the control voltage to output a frequency that is proportional thereto. As a result, the PLL circuit synchronizes an output frequency with an input frequency to synchronize the phases of the internal and external clock signals.
In a DLL circuit, when synchronizing the phases of the external and internal clock signals, the DLL circuit delays the phase of the external clock signal. DLLs are commonly used in DRAM devices. One exemplary DLL circuit is disclosed in U.S. Pat. No. 5,614,855 to Lee. Another exemplary DLL circuit varies a length of a delay line through which the clock signal traverses. Delay line variation can be done using a tapping point for selectively activating a coarse delay chain and a fine delay chain. A phase detector is coupled to the delay line to detect phase differences.
Other phase or Duty-Cycle correction (DCC) circuits can be in the form of a register storing a phase delay value of the internal and external clock signals. The phase delay value is stored at power-down and is loaded at power-down exit to lock the internal and external clock signals. In each of the above clock synchronization circuits, the operation of the clock synchronization circuit and the drive buffer necessary for fanning out the clock signal to the internal circuits of the SDRAM consume a large amount of power.
To conserve power, the SDRAM can be put in a power-down mode when access to the SDRAMs is not needed.
FIGS. 1
to
3
illustrate a conventional memory device, a mode register set and power-down circuit.
FIG. 1
shows a mode register set(MRS) used in the memory device of FIG.
2
. The MRS has address fields A
0
-A
12
in which information (e.g., burst length, burst type (BT), CAS latency, and test mode) for controlling an operation mode of the SDRAM is stored. This information is issued from a central processing unit (CPU) to direct the memory device to operate in different modes. Conventionally, the burst length, the burst type, the CAS latency, and the test mode use the fields A
0
-A
2
, the field A
3
, the fields A
4
-A
6
, and the field A
7
, respectively. The fields A
8
-A
12
are reserved for future use (RFU) and they are generally set to “
0
” during normal operation.
FIG. 2
shows a conventional memory device including components of a memory core
100
having an array of memory cells; a mode register
250
having address fields and operation mode information essentially as described for
FIG. 1
; address decoders
270
and
280
, DLL circuit
230
for generating an internal clock ICLK; clock, address, and data buffers; and a command buffer and decoder
240
. Commands from the CPU or memory controller are received by the command buffer and decoder
240
. The commands are processed and distributed to the pertinent components such as mode register
250
for accessing the memory core
100
. An external clock ECLK is received by clock buffer
210
and buffered clock ECLK
1
is input to DLL circuit
230
through a DLL enable circuit
220
. The DLL circuit
230
generates an internal clock ICLK for driving the memory core
100
. The memory core
100
can be placed in a power down or standby mode, wherein the memory cells within the memory core
100
are not accessed and power is conserved. A power-down command PWDN, issued from the command buffer and decoder
240
, is used to place the memory device in (enter) or out (exit) of a power down mode. This is done by a circuit shown in FIG.
3
. As shown, external clock signal ECLK is buffered by clock buffer
210
and passes through gate
224
to DLL circuit
230
, wherein internal clock ICLK synchronized to ECLK is generated to drive the memory. When it is desired to place the memory device in power-down mode, an active command (entering power down mode) at PWDN (e.g. logic “1”) disables logic gate
224
, which deactivates internal clock signal ICLK output from DLL circuit
230
. Without a clock signal, the memory core
100
cannot operate, it is placed in “power-down” mode, and power consumption is conserved.
In the conventional memory device and power-down mode operation as described for
FIGS. 1
to
3
above, it is noted that although the internal clock signal ICLK is deactivated by disabling the buffered clock ECLKl at DLL enable circuit
220
, the DLL circuit
230
is not turned off. Thus, if further conservation of power is needed, the DLL circuit
230
can also be turned off. It is to be appreciated that the description of a DLL circuit herein is also applicable to other clock synchronization circuits such as PLL and duty-cycle correction circuits. As earlier described, a DLL or PLL includes numerous components such as a phase detector, a charge pump and a VCO. Turning off the clock synchronization circuit accomplishes sizeable power savings. However, with the PLL or DLL turned off, more time is needed to reach phase lock or synchronization between the internal and external clock. Typically, about at least six (6) clock cycles are needed to synchronize the internal clock signal to the external clock signal. Therefore, there exists a trade-off between power savings and the time required to wakeup or exit from power-down mode.
Wakeup or exit from power-down mode brings the device from power down or standby mode back to normal operation. After the power-down exit command, some amount of time is needed before the device can operate normal operations properly. The normal operations can be an active operation (or active command), a read operation (read command), or a write operation (write command), etc.
It is therefore desirous to have a memory device capable of selecting a plurality of power saving modes.
SUMMARY OF THE INVENTION
A circuit for controlling a memory having an array of memory cells arranged in rows and columns, the circuit comprising; at least one address decoder for decoding an address field and outputting decoded addresses for addressing the memory; and a mode register for storing mode register set (MRS) data used for specifying at least one of a plurality of operation modes of the memory based on the address field, wherein the plurality of operation modes include a plurality of power down exit modes.
The circuit preferably further comprising; a clock generator for generating a clock signal in synchronization with an external clock signal for clocking the memory; and a generator enable circuit for directly or indirectly receiving the external clock signal and a power-down comma
Lee Dong-Yang
Lee Jung-Bae
F. Chau & Associates LLP
Le Thong
Samsung Electronics Co,. Ltd.
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