Static information storage and retrieval – Read/write circuit – Bad bit
Patent
1999-09-13
2000-09-26
Elms, Richard
Static information storage and retrieval
Read/write circuit
Bad bit
365201, 3652257, 36523003, G11C 700
Patent
active
061250678
ABSTRACT:
A redundancy architecture for repairing a DRAM includes fuse banks for storing the row addresses of defective rows in sub-arrays of the DRAM. Row decoders activate a redundant row in one of the sub-arrays in response to receiving a row address matching one of the stored defective row addresses and, at the same time, disable a redundant row in the other of the sub-arrays that is arranged in an order complementary to that of the activated redundant row. By activating a redundant row in one sub-array and disabling the corresponding redundant row in an adjacent sub-array, the architecture allows for repairs to be conducted in the one sub-array while a good row in the adjacent sub-array is allowed to continue in operation. Also, since the redundant row used for repairs in the one sub-array is typically nearest the center of the sub-array, the disabled redundant row in the adjacent sub-array is nearest the edge of that sub-array, because it is arranged in an order complementary to that of the redundant row used for repairs. As a result, the disabled redundant row acts as an edge buffer between the primary and redundant rows of the adjacent sub-array and peripheral circuitry.
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Vo Huy T.
Waller William K.
Elms Richard
Micro)n Technology, Inc.
Nguyen Tuan T.
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