Static information storage and retrieval – Read/write circuit – Bad bit
Patent
1998-01-29
1999-10-12
Mai, Son
Static information storage and retrieval
Read/write circuit
Bad bit
36523004, 36523006, G11C 700
Patent
active
059663340
ABSTRACT:
A DRAM array is repairable when the array includes memory cells that are defective because their storage capacitors are unable to retain a sufficient electric charge to properly store "1" and "0" bits. To repair the array, both even and odd row decoders in the array are permanently enabled so that each row address the array receives causes the even row decoder to energize at least one even word line and the odd row decoder to energize at least one odd word line. As a result, at least two memory cells are accessed for each row address so that each "1" or "0" bit is stored as an electric charge in at least two memory cells. By grouping enough memory cells together in this manner to store each "1" and "0" bit, the grouped memory cells are able to retain a sufficient total electric charge as a group to properly store each bit even when individual memory cells in the group are unable to do so.
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Mai Son
Micro)n Technology, Inc.
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