Static information storage and retrieval – Read/write circuit – Data refresh
Reexamination Certificate
2001-06-21
2002-08-27
Mai, Son (Department: 2818)
Static information storage and retrieval
Read/write circuit
Data refresh
C365S200000, C365S230040, C365S230060
Reexamination Certificate
active
06442094
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates in general to memory array repair and, in particular, to devices and methods for repairing memory arrays, such as dynamic random access memory arrays, by storing each individual bit in multiple memory cells in the arrays.
2. State of the Art
In general, Dynamic Random Access Memory (DRAM) arrays store digital information in the form of “1” and “0” bits by storing the bits as electric charges on capacitors. DRAM arrays then retrieve the stored bits by discharging their representative electric charges to a conductor, such as a digit line, and then detecting a change in voltage on the conductor resulting from the discharge. When any of the capacitors in a DRAM array are unable to store a sufficient electric charge to cause a detectable change in voltage on a conductor when discharged to the conductor, any “1” or “0” bits stored as electric charges on those capacitors cannot be retrieved by the array. In this circumstance, the array must be repaired by replacing the failing capacitors with redundant capacitors in redundant rows or columns in the array. If too many of the redundant capacitors also fail, then the array must be discarded.
More specifically, a conventional DRAM array
10
shown in
FIG. 1
stores digital information in the form of “1” and “0” bits by storing the bits as electric charges on storage capacitors
12
,
14
, and
16
in memory cells
18
,
20
,
22
and
24
arranged along word lines (i.e., rows) WL
0
, WL
1
, . . . , and WLm and complementary pairs of digit lines (i.e., columns) D
0
and D
0
*, D
1
and D
1
*, . . . , and Dn and Dn*. Of course, while the DRAM array
10
is shown in
FIG. 1
as having only nine memory cells in order to simplify description, the array
10
typically includes thousands or millions of memory cells.
The DRAM array
10
stores a “1” bit in the memory cell
18
, for example, by energizing the word line WL
0
to activate an NMOS transistor
26
. The DRAM array
10
then applies a “1” bit voltage equal to a supply voltage V
CC
(e.g., 3.3 Volts) to the digit line D
0
, causing current to flow from the digit line D
0
, through the activated NMOS transistor
26
and the storage capacitor
12
, and to a cell plate voltage DVC
2
typically equal to one half the supply voltage V
CC
. As this current flows, the storage capacitor
12
stores positive electric charge received from the digit line D
0
, causing a voltage V
S1
on the storage capacitor
12
to increase. When the voltage V
S1
on the storage capacitor
12
equals the “1” bit voltage on the digit line D
0
, current stops flowing through the storage capacitor
12
. A short time later, the DRAM array
10
de-energizes the word line WL
0
to de-activate the NMOS transistor
26
and isolate the storage capacitor
12
from the digit line D
0
, thereby preventing the positive electric charge stored on the storage capacitor
12
from discharging back to the digit line D
0
.
Similarly, the DRAM array
10
stores a “0” bit in the memory cell
20
, for example, by energizing the word line WL
1
to activate an NMOS transistor
28
. The DRAM array
10
then applies a “0” bit voltage approximately equal to a reference voltage V
SS
(e.g., 0.0 Volts) to the digit line D
0
, causing current to flow from the cell plate voltage DVC
2
, through the storage capacitor
14
and the activated NMOS transistor
28
, and to the digit line D
0
. As this current flows, the storage capacitor
14
stores negative electric charge received from the digit line D
0
, causing a voltage V
S2
on the storage capacitor
14
to decrease. When the voltage V
S2
equals the “0” bit voltage on the digit line D
0
, current stops flowing through the storage capacitor
14
. A short time later, the DRAM array
10
de-energizes the word line WL
1
to de-activate the NMOS transistor
28
and isolate the storage capacitor
14
from the digit line D
0
, thereby preventing the negative electric charge stored on the storage capacitor
14
from discharging back to the digit line D
0
.
The DRAM array
10
stores “1” and “0” bits in the memory cells
22
arranged along the complementary digit lines D
0
*, D*, . . . , and Dn* in a manner similar to that described above, with the exception that the “1” bit voltage for these cells is approximately equal to the reference voltage V
SS
and the “0” bit voltage equals the supply voltage V
CC
.
The DRAM array
10
retrieves “1” and “0” bits stored in the manner described above in the memory cells
18
,
20
,
22
, and
24
by discharging electric charges stored on the storage capacitors
12
,
14
, and
16
to the digit lines D
0
, D
0
*, D
1
, D
1
*, . . . , Dn, and Dn* and then detecting a change in voltage on the digit lines D
0
, D
0
*, D
1
, D
1
*, . . . , Dn, and Dn* resulting from the discharge with sense amplifiers (
0
), (
1
), . . . , and (n).
For example, the DRAM array
10
retrieves the “1” bit stored in the memory cell
18
by first equilibrating the voltages on the digit lines D
0
and D
0
* to the cell plate voltage DVC
2
. The DRAM array
10
then energizes the word line WL
0
to activate the NMOS transistor
26
, causing the positive electric charge stored on the storage capacitor
12
to discharge through the activated NMOS transistor
26
to the digit line D
0
. As the positive electric charge discharges, the voltage on the digit line D
0
rises by an amount V
SENSE
calculated as follows:
V
SENSE
=(
V
S
−DVC
2
)*
C
S
/(
C
D
+C
S
)
where V
S
is the voltage V
S1
, on the storage capacitor
12
, C
S
is the capacitance of the storage capacitor
12
, and C
D
is the capacitance of the digit line D
0
. When the rise in voltage V
SENSE
on the digit line D
0
causes a difference in voltages between the digit lines D
0
and D
0
* to exceed a detection threshold (typically about 150 mVolts) of the sense amplifier (
0
), the sense amplifier (
0
) responds by driving the voltage on the digit line D
0
to the supply voltage V
CC
and by driving the voltage on the digit line D
0
* approximately to the reference voltage V
SS
. Input/output gating circuitry, DC sense amplifiers, and an output buffer (not shown) then transmit these voltages from the digit lines D
0
and D
0
* to external circuitry as a “1” bit.
Likewise, the DRAM array
10
retrieves the “0” bit stored in the memory cell
20
, for example, by first equilibrating the voltages on the digit lines D
0
and D
0
* to the cell plate voltage DVC
2
. The DRAM array
10
then energizes the word line WL
1
to activate the NMOS transistor
28
, causing the negative electric charge stored on the storage capacitor
14
to discharge through the activated NMOS transistor
28
to the digit line D
0
. As the negative electric charge discharges, the voltage on the digit line D
0
falls by an amount V
SENSE
, calculated as described above, where V
S
is the voltage V
S2
on the storage capacitor
14
and C
S
is the capacitance of the storage capacitor
14
. When the drop in voltage V
SENSE
on the digit line D
0
causes the difference in voltages between the digit lines D
0
and D
0
* to exceed the detection threshold of the sense amplifier (
0
), the sense amplifier (
0
) responds by driving the voltage on the digit line D
0
approximately to the reference voltage V
SS
and by driving the voltage on the digit line D
0
* to the supply voltage V
CC
. The input/output gating circuitry, DC sense amplifiers, and output buffer then transmit these voltages from the digit lines D
0
and D
0
* to external circuitry as a “0” bit.
The DRAM array
10
retrieves “1” and “0” bits from the memory cells
22
arranged along the complementary digit lines D
0
*, D
1
*, . . . , and Dn* in the same manner as described above.
DRAM arrays sometimes contain defective memory cells that are unable to reliably store “1” and “0” bits in the manner described above. In some instances, this occurs because the capacitance of the storage capacitors in these memory cells is too small, preventing the capacitors from retaining a sufficient electric charge to cause a
Mai Son
TraskBritt
LandOfFree
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