Error detection/correction and fault detection/recovery – Pulse or data error handling – Replacement of memory spare location – portion – or segment
Reexamination Certificate
2005-06-21
2005-06-21
Lamarre, Guy J. (Department: 2133)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Replacement of memory spare location, portion, or segment
C714S718000, C365S185090
Reexamination Certificate
active
06910161
ABSTRACT:
A method and a device for reducing addresses of faulty memory cells compare addresses of faulty memory cells, as first fault addresses, with addresses of word lines or bit lines which are to be completely repaired, these addresses are referred to as second fault addresses. If the first fault address corresponds to the second fault address, the first fault address is deleted and not further processed. In a second comparison, it is determined, by reference to the number of non-deleted first fault addresses, whether an address of a word line or bit line is used as a new second fault address for the first comparison method. The number of addresses of faulty memory cells are thus reduced.
REFERENCES:
patent: 6725403 (2004-04-01), Schmoelz
Haddad, R. et al.: “Increased Throughput for the Testing and Repair of RAM's with Redundancy”, IEEE, vol. 40, No. 2, Feb. 1991, pp. 154-166.
Kuhn Justus
Weitz Peter
Britt Cynthia
Greenberg Laurence A.
Infineon - Technologies AG
Lamarre Guy J.
Locher Ralph E.
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