Device and method for reading data stored in a semiconductor...

Details Device and method for reading data stored in a semiconductor... Device and method for reading data stored in a semiconductor...

2006-12-12

2006-12-12

Britt, Cynthia (Department: 2138)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Memory testing

C365S187000

Reexamination Certificate

active

07149940

ABSTRACT:
A semiconductor device has multilevel memory cells, each cell storing at least three levels of data each. The multilevel memory cells are arranged so as to correspond to a physical address space, each cell storing 2nlevels of data each expressed by n (n≧2) number of bits (X1, X2,. . . , Xn). A logical address is converted into a physical address of the physical address space. A judgement is made as to whether a logical address space including the logical address matches the physical address space. When matched, the most significant bit X1is specified by performing a single comparison operation using a reference value. The specified bit is output from one of the cells corresponding to the physical address. If not matched, the bits (X2, . . . , Xn) are specified by performing multiple comparison operations using different reference values.

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