Error detection/correction and fault detection/recovery – Data processing system error or fault handling – Reliability and availability
Reexamination Certificate
1998-11-10
2002-03-26
Iqbal, Nadeem (Department: 2184)
Error detection/correction and fault detection/recovery
Data processing system error or fault handling
Reliability and availability
C365S201000
Reexamination Certificate
active
06363500
ABSTRACT:
FIELD OF THE INVENTION
The invention relates to a device and a method for outputting positional information for LSI cells and a recording medium for a positional information output program for LSI cells. More particularly, the invention relates to a positional information output device for LSI cells that outputs, as a fault analysis system for a memory, positional information on a fail cell, a method for outputting the positional information, and a recording medium for a positional information output program for LSI cells.
BACKGROUND OF THE INVENTION
In fault analysis of semiconductor recording devices, such as DRAM (dynamic random access memory) and SRAM (static random access memory), the first step to be done is generally to identify a fail memory cell based on the evaluation of electrical characteristics by means of a memory tester or the like.
Outputting bit maps, such as physical addresses and logical addresses, have hitherto been carried out as a method for detecting and displaying the position of a fail memory cell at a high speed. Up to now, various methods have been proposed in order to improve the visibility of the output of the bit map and to more rapidly and more easily conduct address conversion between the physical address and the logical address.
In order to realize display of a bit map close to an actual device, for example, Japanese Patent Laid-Open No. 105544/1981 has proposed a system fault analyzing method wherein a physical address and a logical address are recorded as a pair, Japanese Patent Laid-Open No. 131470/1989 has proposed an LSI fault analyzer that displays, as layout display, simulation results in comparison with an actual device, and Japanese Patent Laid-Open No. 278556/1992 has proposed an LSI appearance fault analyzing system wherein a fault from an appearance tester is put on a bit map.
On the other hand, in order to facilitate conversion from the logical address to the physical address, for example, Japanese Patent Laid-Open No. 43429/1995 has proposed a physical address conversion circuit wherein address conversion is carried out using a hardware.
The conventional positional information output device for LSI cells will be briefly explained with reference to a fault analysis system for a semiconductor memory, by way of example, proposed in Japanese Patent Laid-Open No. 289477/1992.
A fail bit analyzing system comprises a memory tester, a positional information section for a fail memory cell, and a substantial address array conversion section. The memory tester detects electrical positional information on a fault analysis memory cell, and the positional information section for a fail memory cell stores the information in a logical address space. In the substantial address array conversion section, the fail memory cell identified by the logical address space is converted to substantial address information according to an actual layout of a semiconductor memory.
The substantial address array conversion section uses a part of layout information read from an auxiliary memory through a host CPU to perform conversion from logical address information to substantial address information.
The conventional positional information output device for LSI cells has the following problems.
Firstly, output information on the bit map is unsatisfactory for clearly understanding the state of a fail bit. This is because, in general, the output of the bit map is only for the physical address. For example, for DRAM, when a reflected bit line system is used, since the array of physical address constituted by sense AMP and word line is different from the array of the capacity section storing memory cell information, it is difficult to clearly understand the state of a fail bit through output of the physical address only. Further, for some causes of fault, display of logical address can provide more clear understanding of a fail bit than display of physical address.
Secondly, the bit map cannot be displayed by several methods.
In displaying the bit map by several methods, it is necessary to previously provide mutual address conversion formulae. The address conversion is generally expressed by Boolean algebra. Therefore, it is generally difficult to determine a function of inverse conversion.
SUMMARY OF THE INVENTION
Accordingly, it is an object of the invention to provide a positional information output device for LSI cells, a method for outputting the positional information, and a recording medium for a positional information output program for LSI cells that enable the state of a fail bit expressed by outputting a bit map to be more clearly understood at the time of a fault analysis of a semiconductor memory and, at the same time, can reduce the number of conversion formulae which should be previously provided for address conversion of the bit map.
According to the first feature of the invention, a positional information output device for LSI cells, adapted for outputting information on the position of a fail cell which has been found to be defective through an electrical test on a semiconductor memory, comprises address conversion means for converting one address array information to other address array information, permitting the positional information on a cell to be output as a plurality of types of address array information.
In the positional information output device having the above construction according to the invention, in outputting the positional information of a fail cell which has been found to be defective through an electrical test on a semiconductor memory, the address conversion means converts one address array information to other address array information, making it possible to output the positional information of the cell as a plurality of types of address information based on at least address array information before the conversion and address array information after the conversion.
It is a matter of course that when the address conversion means converts one address array information to a plurality of types of address array information, the plurality of types of address array information may be output.
For example, a conversion formula for conversion from a physical address to a logical address and a conversion formula for conversion from a physical address to an address in a capacity section storing memory cell information are provided, and the address conversion means uses the above conversion formula to output and display the positional information of a fail cell in a desired type of address.
Various types of address array information may be adopted for conversion address. For example, in the positional information output device for LSI cells, the address conversion means may convert cell information to address array information in a capacity section that stores cell information.
In this construction, in outputting the positional information of the cell as a plurality of types of address array information, the address conversion means converts cell information to address array information in a capacity section storing cell information, and the address array information in the capacity section is output.
Since the address array information in the capacity section is not always an orthogonal coordinate, in the positional information output device for LSI cells, the address conversion means may be constructed so that, in outputting the address array information in the capacity section storing the cell information, the address conversion means outputs address array information reflecting actual memory dell array form of the device.
In this construction, when the address conversion means outputs address array information in the capacity section storing cell information, the address conversion means reflects the memory cell array form of an actual device and outputs the address array information according to the form.
In the actual device, there are various memory cell array forms. For example, in the positional information output device for LSI cells, the memory cell array form may be parallelogrammic.
In this construction, since the memory cell
Iqbal Nadeem
NEC Corporation
Scully Scott Murphy & Presser
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