Device and method for modular multiplication

Cryptography – Communication system using cryptography – Symmetric key cryptography

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708491, 708492, G06F 738

Patent

active

061513938

ABSTRACT:
A method and apparatus are disclosed for performing modular multiplication. Modular multiplication in accordance with the present invention includes precalculating a 2's complement of a given modulus and multiples of the 2's complement and calculating a total magnitude of end-around carries during the modular multiplication. The calculated multiples are selected depending on the total magnitude of the end-around carries, and the selected multiples are added. The disclosure includes array structures in accordance with the present invention. The invention includes an algorithm designed for Rivest-Shamir-Adelman (RSA) cryptography and based on the familiar iterative Homer's rule, but uses precalculated complements of the modulus. The problem of deciding which multiples of the modulus to subtract in intermediate iteration stages has been simplified using simple look-up of precalculated complement numbers, thus allowing a finer-grain pipeline. Regularity and local connections make the algorithm suitable for high-performance array implementation in FPGA's (field programmable gate arrays) or deep submicron VLSI's.

REFERENCES:
patent: 5210710 (1993-05-01), Omura
patent: 5513133 (1996-04-01), Cressel et al.
patent: 5742530 (1998-04-01), Gressel et al.
patent: 5987489 (1999-11-01), Monier

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