Electrical computers and digital processing systems: memory – Storage accessing and control – Hierarchical memories
Reexamination Certificate
1998-12-23
2002-09-10
Gossage, Glenn (Department: 2187)
Electrical computers and digital processing systems: memory
Storage accessing and control
Hierarchical memories
C711S147000, C711S205000, C709S203000
Reexamination Certificate
active
06449696
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to an electronic computer system and more specifically to a method and device for control of the electronic computer system which results in efficient prefetching of data.
2. Description of the Related Art
With the advent and proliferation of computer systems having a client-server architecture, the size of electronic computers is being reduced relative to the size of previous-generation, general-purpose computers. In client-server systems, the client computers typically include personal computers (PCs), and the management cost for managing the client-server system must be re-estimated to take into account the cost of managing each personal computer (herein after referred to as PC). To reduce the management cost for PCs, a system is employed in which application software or user data is stored in the server and each PC (in its role as a client) accesses the server to use the application software or data stored therein. The server and the PCs are interconnected by network, and are referred to collectively as a network computing system.
In the network computing system as described above, and in most electronic computer systems built around a server, it appears to each client computer (or PC) that the application software or the user data being accessed is stored in or on the hard disk of the respective PC. Also in the network computing system described herein above, a disk sub-system may be connected to the server and a hard disk device of this sub-system may used as a cache.
The performance of a computer system as a whole largely depends on the access speed to the frequently used application software or user data, and particularly to the input/output (IO) performance of a disk sub-system storing the application software or user data. In this system, data is read from the disk device of the disk sub-system and stored in the cache. However, to speed up processing, if the data is already stored in the cache when the access request for the data is made, the data is read directly from the cache.
The above described method is referred to as prefetch processing. Japanese Patent Laid-Open Publication No. SHO 61-175721 discloses prefetch processing in detail. More particularly, the foregoing publication describes an input/output control device capable of prefetching data to be read out, in which an input/output operation request issued by a central processing unit to the input/output control device is statistically analyzed, data is read from an auxiliary storage device of the central processing unit and stored in a built-in, high speed storing unit of the input/output control device. The reading of the data is performed based on information concerning files stored in an auxiliary storage device determined by the central processing unit and on the result of the already mentioned statistical analysis. By doing this, the required data is kept ready in the high speed storing unit at the point in time when a request for reading the data is issued from the central processing unit to the input/output control device. Accordingly, an input operation can be completed within a shorter period of time because the data does not have to be read from the auxiliary storage device in association with a request for the input operation.
Japanese Patent Laid-Open Publication No. HEI 6-332629 discloses a signal processing unit exclusively for magnetic disks. This unit comprises sections such as an access address detection/determination circuit, a buffer control circuit, and a main control section. The access address detection/determination circuit determines whether access to successive addresses on a magnetic disk is made or not and also counts the addresses. The buffer control circuit reads data stored on the magnetic disk regardless of whether a host command has been issued. The main control section determines whether the read data is to be sent to an upper (such as a host) level device while simultaneously storing the data in a data buffer or the read data is to be sent to an upper level device without storing the data in the data buffer and issuing an instruction according to the determination. The main control section also has an access optimizing control function executing statistical analysis of the selecting operation in each of the other sections in response to an access from an upper device, and selects and adapts an optimal control method for access from an upper device based on a result of the above statistical processing.
Further, Japanese Patent Laid-Open Publication No. HEI 7-104940 discloses a disk device. This device includes a reading unit, a transfer unit, an inferring unit, a prefetching unit, a storing unit, and a control unit. The reading unit reads the data recorded on a disk according to a command received from a host control unit. The transfer unit transfers the read data to the host control unit. The inferring unit infers a read command which the host control unit might issue next. The prefetching unit prefetches the data from the disk based on the output of the inferring unit. The storing unit stores the data read by the prefetching unit and/or the reading unit. The control unit controls the disk device its entirety.
The inferring unit includes a first determining unit that determines whether a command received previously and a currently-received command are read commands, and a second determining unit that determines whether there is continuity between an ending address of the previous read command and a beginning (or header) address of a current read command. The host control unit infers a read command to be transmitted next and a beginning address of the read command according to a result of determination by the first and second determining units.
In association with the recent scale-up of application software, a number of input and output (hereinafter referred to as I/O) requests are simultaneously and concurrently issued from a plurality of clients connected to a server, and an increasingly larger number of I/O requests for execution modules are reported to a disk device residing on the server side of the client-server computer system. Accordingly, a processing algorithm enabling efficient processing in a device which controls the disk device is needed.
A hit ratio of data stored in a cache is dependent whether the data is prefetched regularly or based upon estimates. In the input/output control device disclosed in Japanese Patent Laid-Open Publication No. SHO 61-175721, however, the type of analytical methods used to analyze the I/O operation requests issued from the central processing unit to the I/O control device are unclear, as is whether the data is prefetched regularly or based upon estimates. For this reason, whether a sufficient hit ratio for data stored in the cache can be obtained is ambiguous.
In the signal processing unit disclosed in Japanese Patent Laid-Open Publication No. HEI 6-332629 discussed earlier, as well as in Japanese Patent Laid-Open Publication No. HEI 7-104940, since data at successive addresses is prefetched and stored in the cache, a requested reading of data requiring prefetching data stored at non-successive addresses cannot be executed effectively, and a sufficient hit ratio is not obtained.
Also, in the disk device disclosed in Japanese Patent Laid-Open Publication No. HEI 7-104940, data stored at successive addresses is prefetched and stored in the cache, a requested reading of data issued requiring prefetching data stored at non-successive addresses cannot be executed effectively, and a sufficient hit ratio is not obtained.
Even if data stored at non-successive addresses are prefetched on the basis of some sort of regularities or estimations, time is required for reading ahead to skip to a non-successive address, namely a seek time is generated, so that data cannot efficiently be prefetched, and high speed reading of data by prefetching may not be realized.
SUMMARY OF THE INVENTION
The present invention was made in the light of the circumstances as describ
Fujitsu Limited
Gossage Glenn
Staas & Halsey , LLP
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