Device and method for information processing

Details Device and method for information processing Device and method for information processing

2005-08-16

2005-08-16

Chace, Christian P. (Department: 2189)

Electrical computers and digital processing systems: memory

Address formation

Slip control, misaligning, boundary alignment

C711S214000, C711S217000, C711S220000, C365S230030, C365S236000, C365S238500

Reexamination Certificate

active

06931508

ABSTRACT:
In an information processing device, a first address adder generates a first address representing a target for write of data or a storage location of data to be read. A second address adder generates a second address by adding 8 to the first address. First to seventh selectors appropriately select either the first address or the second address, and supply the selected address to first to seventh memory areas, respectively. An eighth memory area is supplied with the first address.

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“Method for Handling Unaligned Operands That Extend Across Memory Protection Boundaries in a Microprocessor” IBM Technical Disclosure Bulletin, IBM Corp. New York, US, vol. 37, No. 4B, Apr. 1, 1994, pp 597-598.

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