Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2000-06-12
2003-07-01
Siek, Vuthe (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000, C716S030000
Reexamination Certificate
active
06587996
ABSTRACT:
FIELD
The invention generally relates to a device and method to increase fault tolerance using scan insertion techniques around synchronous memory. More particularly, the invention relates to a device and method to enable increased fault coverage using scan insertion techniques around synchronous random access memory (RAM) isolated by a built-in self test (BIST) wrapper.
BACKGROUND
Advances in chip manufacturing technology have enabled rapid progress to be seen in the speed, size and cost of computer systems. At one time it would have been considered impossible to put a sizable amount of memory on a single chip. Today not only is it possible to have a large amount of memory on a single chip, it is also possible for the circuitry for a device or a communications controller to be placed on a single chip and also have a significant amount of embedded memory in the form of SRAM on the same chip.
However, as the ability to pack more circuits, transistors and memory on a single chip has increased, so has the complexity of the logic and circuitry used in these chips. With the rapid increase in the complexity of the chip, software has been developed to aid the electrical engineer in the design and testing of the logic used in the design. These software chip development tools have made the task of designing large complex chips easier since the software can simulate the logic and design errors can be more easily detected.
However, the software chip development tools are not perfect and a simulation, even though extremely useful, is not a substitute for building a prototype. Therefore, when the design of a complex chip is finalized, prototypes are built and tested. However, these chips are very complex and by merely checking the input to the chip and the output from the chip, it is not possible to identify the specific design or manufacturing error on the chip.
Therefore, most large chip designs use automatic scan insertion techniques built directly in the chip to provide high levels of fault coverage. Fault coverage is the ability to detect when an internal node within the chip is either “stuck at one” or “stuck at zero.” Such faults may be due to either design errors or manufacturing problems. These automatic scan insertion techniques will typically insert a scan chain directly on the chip at critical locations. One such scan chain is shown in
FIG. 1
in which the scan chain is inserted into the chip logic by connecting all the flip-flops together. Carefully selected patterns are then shifted into the scan chain which are shifted out on the leading edge of the next clock cycle and checked for accuracy.
The scan chain shown in
FIG. 1
uses multiplexer (MUX)
10
to select either scan in signal
70
or normal in signal
60
for transmission to flip-flop
20
via link
90
. A clock signal
80
is used to synchronize flip-flops
20
and
50
. The flip-flop
20
then generates a scan out signal
120
and a normal out signal
130
. The normal out signal
130
is feed into the logic cloud
30
which generates a normal in signal
100
that feeds into MUX
40
. During the operation of a scan chain test the scan out signal
120
propagates a signal that directly or indirectly connects to scan in signal
110
. When a scan test is being performed the MUX
40
selects input from scan in
110
. A link
140
provides a signal to flip-flop
50
that supplies a normal out signal
160
and a scan out signal
170
which also provides the results of the scan chain test.
The scan chain shown in
FIG. 1
serves well to test most circuitry logic. However, where, as shown in
FIG. 2
, a synchronous 1 or 2 port random access memory (RAM)
220
(hereinafter “RAM”) is embedded in circuit
320
, then it is not necessarily the case that RAM
220
will deliver the same output data via link
300
to logic cloud
230
as input data from flip-flop
200
via link(s)
250
provided. This is due to the possibility that a write may occur via write data link
260
, write address link
270
, and write enable link
280
which is separate and distinct from a read occurring via read address
290
. Thus, the data output from logic cloud
230
via links
310
to flip-flop
240
may not be the same as that input via flip-flop
200
.
Therefore, what is needed is a device and method that will enable the testing of a circuit having embedded RAM in a single chip. This device and method should have no impact on normal operation of the circuit in the chip and should enable the operation of a scan chain to test the circuit. Further, this device should occupy a minimal amount of space on the chip and thereby allow for as much space as possible to be available for normal operations. Also, this device and method should not impact the execution speed of the chip in normal operations.
REFERENCES:
patent: 5592493 (1997-01-01), Crouch et al.
patent: 5696770 (1997-12-01), Lo
Collins Brian M.
Reohr, Jr. Richard D.
Antonelli Terry Stout & Kraus LLP
Intel Corporation
Levin Naum
Siek Vuthe
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