Electrical computers and digital processing systems: memory – Storage accessing and control – Hierarchical memories
Reexamination Certificate
2007-02-06
2007-02-06
Lane, Jack A. (Department: 2185)
Electrical computers and digital processing systems: memory
Storage accessing and control
Hierarchical memories
Reexamination Certificate
active
10728639
ABSTRACT:
A device and method for handling Multiprotocol Label Switching (MPLS) label stacks. An incoming label mapping (ILM) table is stored in a first memory. A received packet's label stack is accessed, and an entry corresponding to a top label of the stack is read from the ILM table. A number of other entries are also read from the ILM table, and these other entries are cached in a second memory.
REFERENCES:
patent: 6925081 (2005-08-01), Meda
patent: 2002/0003797 (2002-01-01), Rautenberg
patent: 2002/0060985 (2002-05-01), Lee et al.
patent: 2003/0002444 (2003-01-01), Shin et al.
patent: 2003/0053464 (2003-03-01), Chen et al.
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IETF RFC 2702, “Requirements for Traffic Engineering Over MPLS”, Sep. 1999, 1-28 pgs.
IETF RFC 3031, “Multiprotocol Label Switching Architecture”, Jan. 2001, 1-57 pgs.
IEFT RFC 3036, “LDP Specification”, Network Working Group, Jan. 2001, 1-124 pgs.
Blakely , Sokoloff, Taylor & Zafman LLP
Lane Jack A.
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