Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2006-09-26
2006-09-26
Do, Thuan (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000, C716S030000
Reexamination Certificate
active
07114139
ABSTRACT:
A plurality of blocks are optimally placed within a short process time while minimizing the exceeding of the delay time. Input means receives information on a logic circuit having a hierarchical structure including a plurality of blocks, and RTL estimation means calculates a delay time in the blocks in advance. Path detection means detects a timing path extending via a plurality of blocks, and delay calculation means calculates a delay value while assuming that the inter-block interconnect length is zero. Delay margin setting means sets a delay margin obtained by subtracting the delay value from a predetermined delay time. The delay margin forms a part of an objective function as a weight on the virtual interconnect length between each of the inter-block terminal pairs in the placement process, and the blocks are automatically placed by using the objective function.
REFERENCES:
patent: 6038691 (2000-03-01), Nakao et al.
patent: 6658628 (2003-12-01), Landy et al.
patent: 6684374 (2004-01-01), Ito et al.
patent: 2000-200835 (2000-07-01), None
patent: 2000-339364 (2000-12-01), None
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