Electrical computers and digital processing systems: support – Computer power control
Reexamination Certificate
1997-12-22
2001-06-05
Sheikh, Ayaz (Department: 2155)
Electrical computers and digital processing systems: support
Computer power control
C713S323000, C713S324000, C713S340000, C345S520000, C361S086000
Reexamination Certificate
active
06243817
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to a computer and, more particularly, to a bus interface unit having a plurality of input buffers which can be selectively deactivated depending on the current power state of the computer and/or activity upon a central processing unit (“CPU”) local bus.
2. Description of the Related Art
Power consumption in an electronic device is always a significant concern. Longevity of the power supply, heat dissipation, physical size, weight, efficiency and other related characteristics are paramount in designing the electronic device. These characteristics become exceptionally critical when the device is a self-sufficient portable unit.
A portable unit is one in which power is supplied from a battery during times when the unit is decoupled from its main power source, e.g., a 110 volt ac supply. In some instances, the battery functions as an auxiliary power source to ensure critical circuits are kept alive and to retain information stored in memory. In other instances, the battery functions as the main power source to fully power the device in its operational state.
Various types of portable units can be powered from a battery including, for example, a computer. Modern portable computers are called upon to perform at increasingly higher levels. For example, a high performance portable computer may employ a high speed CPU and multiple buses between the CPU and numerous input/output devices. Multiple buses may include a CPU local bus connected directly to the CPU, a peripheral bus connected to slower input/output devices, and a mezzanine bus connected between the CPU local bus and the peripheral bus. The peripheral bus can be classified as, for example, an industry standard architecture (“ISA”) bus, an enhanced ISA (“EISA”) bus or a microchannel bus. The mezzanine bus can be classified as, for example, a peripheral component interface (“PCI”) bus to which higher speed input/output devices can be connected.
Coupled between the various busses are bus interface units. According to somewhat known terminology, the bus interface unit coupled between the CPU bus and the PCI bus is often termed the “north bridge”. Similarly, the bus interface unit between the PCI bus and the peripheral bus is often termed the “south bridge”.
The north bridge bus interface unit must accommodate the high speed clocking cycles of the CPU. In many instances, the internal clock of a modern day CPU will transition at rates exceeding several hundred MHz. In order to accommodate this speed, signal swing within the CPU bus must be somewhat limited. For example, complimentary metal oxide semiconductor (“CMOS”) signal swings are too large even though CMOS technology consumes minimal power.
Recently, another standard for electrical signal transmission called Gunning Transceiver Logic (“GTL”) has been devised which can accommodate the higher speeds of modern CPU buses. Typically, a GTL signal will extend minimally above and below a reference voltage. In order to illustrate GTL usage in a modern Pentium® Pro CPU bus operating in excess of 50 MHz, GTL signal swings are typically constrained less than 200 millivolts from a reference voltage.
Smaller voltage swings may allow higher clock speeds. However, a GTL bus is an “open-collector” bus which generally requires pull-up resistors near terminating ends of each bus conductor. Significant power consumption is due, in part, to the operation of the pull-up resistors. In addition, GTL or GTL+ advocated by Intel Corporation requires a level-sensitive differential amplifier coupled to receive the GTL signals. Regardless of whether the signal is active or inactive, the differential amplifier nonetheless remains on and consumes power. Embodied upon the north bridge and associated with each conductor of the CPU bus is a constantly on differential amplifier.
It would be desirable to produce a portable computer which can accommodate a high speed CPU bus using, for example, differential signals set forth possibly in a GTL, GTL+, 1394 or serial link format. However, to produce a viable portable computer having the aforesaid performance characteristics, a mechanism must be derived which can monitor the CPU bus and periodically reduce power consumption in the critical elements of the portable computer. Namely, an improvement is needed for dynamically reducing power consumption of the differential amplifiers within the north bridge when the differential signals sent across the CPU bus are inactive. Reducing power consumption in a portable computer having a bus which employs differential signals would help extend the battery life of the computer.
SUMMARY OF THE INVENTION
The problems outlined above are in large part solved by an improved power management technique. Power management involves reducing power in the north bridge by disconnecting power to differential input amplifiers when they are not receiving active signals. A mechanism is used to monitor the CPU bus and signals within that bus. If signals appear, they generally appear in relation to a particular bus activity. That is, all transactions of a CPU bus are related to a single bus request, beginning with bus arbitration, and the assertion of an address strobe, ADS#. Transactions are driven to transfer data, to inquire about or change cache state, or to provide the system with information. Thus, a transaction may contain numerous phases, wherein a phase uses a specific set of signals to communicate a particular type of information. For example, the Pentiumt® Pro CPU bus protocol involves up to six phases: arbitration, request, error, snoop, response, and data transfer.
By monitoring signals associated with specific transactional phases, it is determined that many of the input buffers within the north bridge can be periodically turned off (i.e., disconnected from power or ground). For example, when signals attributed to a snoop phase are active, then signals associated with all other phases will be inactive, if the phase attributed to those signals do not overlap with the snoop phase. This allows an opportunity to disconnect power to all input buffers within the north bridge except those receiving active signals, or except those which are needed to receive the initial address strobe, ADS#. Accordingly, when signals associated with a particular phase are active, only the differential amplifiers which receive those signals are powered, along with differential amplifiers configured to receive the original request phase signals should they occur.
The present mechanism can also monitor the power state of the computer to determine if the computer is in a run state or a sleep state. If in a sleep state (including, e.g., idle state, standby state and hibernation state), then the CPU bus is monitored for a stop clock signal (STPCLK_) which indicates entry into the sleep state. If the stop clock signal is encountered, then all input buffers and/or differential amplifiers coupled to receive input signals from the CPU bus are disconnected from power. As defined herein below, power is the upper or lower power supplies, including V
DD
, V
CC
and/or ground.
Broadly speaking, the present invention contemplates a computer. The computer comprises a CPU and a bus coupled to the CPU. The bus comprises a plurality of conductors segregated into sets of conductors. Each set of conductors accommodates a plurality of signals which are active only during a discrete transaction phase of the bus. The computer further comprises a bus interface unit coupled to the CPU bus. The bus interface unit comprises a plurality of input buffers segregated into sets of input buffers coupled to respective sets of conductors. The sets of input buffers are selectively disconnected from power during times in which the plurality of signals forwarded thereto are inactive.
According to one embodiment, the transferred signals are classified according to a transaction phase of activity upon the CPU bus. A set of input buffers can be selectively disconnected from power by forwarding a disable si
Maguire David J.
Melo Maria L.
Reif James R.
Compaq Computer Corporation
Conley & Rose & Tayon P.C.
Daffer Karen L.
Jean Frantz B.
Sheikh Ayaz
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