Electrical computers and digital data processing systems: input/ – Input/output data processing – Peripheral configuration
Reexamination Certificate
2000-03-16
2003-07-22
Gaffin, Jeffrey (Department: 2182)
Electrical computers and digital data processing systems: input/
Input/output data processing
Peripheral configuration
C710S015000, C710S018000, C710S043000
Reexamination Certificate
active
06598096
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to a device and a method for controlling packet transfer, and more particularly, to a packet transfer controller that complies with the IEEE 1394 interface standard.
The IEEE 1394 standard is used in controllers that transfer large and continuous amounts of data, such as dynamic image data, at high speeds. According to this standard, isochronous data transfer is performed every 125 &mgr;s. An irregularity in the transfer timing of the dynamic image data results in insufficient continuity of the reproduced dynamic image. This causes the reproduced dynamic image to lack reality. Thus, isochronous transfer is performed by dividing the dynamic image data into a plurality of packets and continuously transferring the packets at equal intervals. This allows the reproduced dynamic image to look real.
Hot plugging is standardized by the IEEE 1394 and refers to the connection or disconnection of one or more devices (nodes) to an IEEE 1394 bus while power is being supplied to the bus. Further, hot plugging results in topology changes.
When the topology changes, a prior art transfer controller performs initialization or bus reset to map the topology even while packets are being transferred. The initialization interrupts the transfer of packets and interferes with the reproduction of real looking dynamic images.
SUMMARY OF THE INVENTION
It is an object of the present invention to provide a device and a method for controlling packet transfer that prevents bus reset during data transfer.
To achieve the above object, the present invention provides a packet transfer device used to transfer data between a plurality of nodes. The packet transfer dexice includes a processor for storing a series of data in a plurality of packets. The series of data is divided into a plurality of blocks, each stored in one of the packets. The packets are transferred at equal intervals. An initialization prohibition unit prohibits initialization of the nodes during the transfer of the data.
Another aspect of the present invention provides a packet transfer method for transferring a series of data between a plurality of nodes. The method includes the steps of dividing the series of data, storing the divided data in a plurality of packets, sequentially transferring the packets at equal intervals, and prohibiting initialization of the nodes during the transfer of the packets.
A further aspect of the present invention provides a packet transfer controller for controlling the transfer of a series of data packets between nodes connected to each other by a bus cable. The nodes and the bus cable define a bus topology. The controller includes a socket for mating with a plug of the bus cable. When the plug mates with the socket, the bus cable is electrically connected to the controller. A processing circuit, connected to the socket, transmits packets to and receives packets from the bus cable. A host processor is connected to the processing circuit to receive packets therefrom and transmitting packets thereto. A monitor circuit monitors the transfer of the series of data packets between the nodes. While a series of packets is being transferred between the nodes, the monitoring circuit inhibits reinitialization caused by changing the bus topology.
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Oi Kenji
Shimizu Takashi
Takase Hiroshi
Ueno Hirotaka
Arent Fox Kintner & Plotkin & Kahn, PLLC
Gaffin Jeffrey
Sorrell Eron
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